Zobrazeno 1 - 10
of 95
pro vyhledávání: '"Min, Yinghua"'
Publikováno v:
Journal of Business & Industrial Marketing, 2023, Vol. 39, Issue 2, pp. 407-422.
Externí odkaz:
http://www.emeraldinsight.com/doi/10.1108/JBIM-01-2023-0042
Autor:
Min Yinghua
Publikováno v:
Journal of Computer Science and Technology. 17:113-117
Register Transfer Level (RTL) Automatic Test Pattern Generation, (ATPG) has been of wide concern for two decades. Meanwhile gate-level ATPG has made remarkable progress in dealing with large circuits. An argument is then posed. Do we need RTL ATPG in
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::82ccc22531c771b4074903d9c83e3361
https://doi.org/10.1007/bf02962203
https://doi.org/10.1007/bf02962203
Publikováno v:
Journal of Computer Science and Technology. 16:474-479
With the popularization of network applications and multiprocessor systems, dependability of systems has drawn considerable attention. This paper presents a new technique of node grouping for system-level fault diagnosis to simplify the complexity of
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::53229fc57a3da60a45f6e2dad1097fda
https://doi.org/10.1007/bf02948966
https://doi.org/10.1007/bf02948966
Autor:
Min Yinghua, Li Jintao
Publikováno v:
Journal of Computer Science and Technology. 5:164-174
A Product-oriented test-pattern generation strategy for Programmable Logic Arrays (PLAs) is presented. First the personality of products is discussed. Products are divided into several categories to speed up the test generation. This strategy aims at
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::dc4d9a638f626777f4f6410f101c0658
https://doi.org/10.1007/bf02943422
https://doi.org/10.1007/bf02943422
Publikováno v:
ASICON 2001. 2001 4th International Conference on ASIC Proceedings (Cat. No.01TH8549).
Multiple-modular redundancy has found many applications in fault-tolerant systems with high reliability and safety requirements. Concurrent error detection or correction circuits and fail-safe I/O circuits (such as decoders, comparators, and voters)
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::34d8e8860a57fbd165e96e970666003f
https://doi.org/10.1109/icasic.2001.982627
https://doi.org/10.1109/icasic.2001.982627
Akademický článek
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Publikováno v:
Journal of Computer Research and Development. 44:479
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::a87501fca4660bae560ebca05e7366d1
https://doi.org/10.1360/crad20070317
https://doi.org/10.1360/crad20070317
Autor:
Min, Yinghua, Stroud, Charles
Publikováno v:
In VLSI Test Principles and Architectures 2006:1-36
Akademický článek
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Publikováno v:
2001 4th International Conference on ASIC Proceedings ASICON 2001 (Cat. No.01TH8549); 2001, p570-573, 4p