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Publikováno v:
2013 25th International Symposium on Power Semiconductor Devices & IC's (ISPSD).
In this paper, we discuss the fundamental design tradeoff among specific on-resistance (Ron, sp), gate charge (Cgg), quasi-saturation, and reliability characteristics for an integrated high voltage LDMOS. A novel patterned gate design is proposed and
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::f5d63a856c21cbdab2f4eff22882bb93
https://doi.org/10.1109/ispsd.2013.6694446
https://doi.org/10.1109/ispsd.2013.6694446
