Zobrazeno 1 - 10
of 17
pro vyhledávání: '"Mike Peng Li"'
Autor:
Ahmad Khairi, Amir Laufer, Ilia Radashkevich, Yoel Krupnik, Jihwan Kim, Tali Warshavsky Grafi, Ajay Balankutty, Yaniv Sabag, Yoav Segal, Udi Virobnik, Mike Peng Li, Itamar Levin, Yosef Ben Ezra, Ariel Cohen
Publikováno v:
IEEE Open Journal of the Solid-State Circuits Society, Vol 4, Pp 265-276 (2024)
System considerations, circuit architecture, and design implementation of wireline and linear optics transceivers capable of supporting data-rates beyond 200 Gb/s are presented. We showcase the silicon results of a transceiver designed in the advance
Externí odkaz:
https://doaj.org/article/1a61bad89f914316847e29265c5dbfa5
Publikováno v:
IEEE Transactions on Electromagnetic Compatibility. :1-11
Jitter decomposition is a key tool to identify root causes of jitters in a high-speed digital communication system. It is a huge challenge in balancing the test cost and precision for conventional decomposition methods implemented in instruments wher
Publikováno v:
IEEE Communications Magazine. 51:130-136
This article provides an overview of some of the work that is ongoing in the IEEE P802.3bj 100 Gb/s Backplane and Copper Cable Task Force. The task force is standardizing Ethernet at 100 Gb/s over a 4-lane backplane channel as well as across a 4-lane
Autor:
Mike Peng Li
Publikováno v:
IEEE Transactions on Advanced Packaging. 32:290-297
The bandwidths of high-speed input/output (I/O) links keep increasing to meet the ever-growing demands for high-speed communications. The data rates for the leading edge high-speed I/O standards have already increased to around 10 Gb/s, including 10
Publikováno v:
VTS
Recent analog designers do think about measurement at design time. Analog design-for-measurement is a real success, not based on test research but based on designers' incorporation of calibration methods to ensure that their circuits work within spec
Publikováno v:
CICC
As the high-speed I/O (HSIO) and serial link data rate keeps increasing, the requirements for accuracy and advanced capabilities of its modeling and simulation techniques get more stringent. Emerging requirements such as comprehending process, voltag
Publikováno v:
ITC
In high speed data communications, timing jitter and voltage noise analyses often depend on mathematical models to predict long-term reliability of the system, typically merited by a low bit error ratio (BER). Many methods involve the extrapolation o
Publikováno v:
ITC
Moving to the latest submicron node is required for digital scaling but causes many challenges for analog design. Additionally, scaling pushes the need for higher bandwidth. Data rates up to 28Gbps require effectively dealing with random variations a
Publikováno v:
ITC
We propose a new method for modeling and quantifying bounded Gaussian jitter (BGJ), as well as bounded Gaussian noise (BGN). The validity and accuracy of the method are illustrated and verified both in theory and experiments. We then demonstrate the
Autor:
Sergey Shumarayev, Mike Peng Li
Publikováno v:
CICC
We first review the signaling and jitter requirements for emerging high-speed wireline communication standards at ∼10 Gbps, including CEI 11G, XLAUI/CAUI, XFI, and SFP+. We then present an FPGA transceiver architecture and subsystem/circuit blocks