Zobrazeno 1 - 8
of 8
pro vyhledávání: '"Mika Nyström"'
Autor:
Alain J. Martin, Mika Nyström
Publikováno v:
Proceedings of the IEEE. 94:1089-1120
SoC design will require asynchronous techniques as the large parameter variations across the chip will make it impossible to control delays in clock networks and other global signals efficiently. Initially, SoCs will be globally asynchronous and loca
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::efe2f92e72c1a8c6ce510735eb88a130
https://doi.org/10.1109/jproc.2006.875789
https://doi.org/10.1109/jproc.2006.875789
Publikováno v:
IEEE Design & Test of Computers. 20:9-17
We trace the evolution of Caltech asynchronous processors from a simple proof of concept, to a high-performance MIPS-like processor using a different buffer circuit for better performance, to the latest 8051 clone targeting low-energy operation. We d
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::74f7a564d49698b02dd6080c2c39716c
https://doi.org/10.1109/mdt.2003.1246159
https://doi.org/10.1109/mdt.2003.1246159
Publikováno v:
Timing Issues in the Specification and Synthesis of Digital Systems
This paper studies the problem of transistor sizing of CMOS circuits optimized for energy-delay efficiency, i.e., for optimal Etn where E is the energy consumption and t is the delay of the circuit, while n is a fixed positive optimization index that
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::a0fbe3a9398d6ee6772647ce7f566cc7
https://doi.org/10.21236/ada437313
https://doi.org/10.21236/ada437313
Publikováno v:
ASYNC
Asynchronous pulse logic (APL) is an adaptation of quasi delay-insensitive (QDI) techniques using easily controllable timing assumptions that speed up the handshakes without changing the high-level dataflow model. We review the basic properties of AP
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::0f753920c752a23bf1a54d35ded16e05
https://doi.org/10.1109/async.2004.1299306
https://doi.org/10.1109/async.2004.1299306
Autor:
Andrea Tura, E. Ou, J.T. Tong, Papadantonakis Karl S, Paul I. Pénzes, Jim Pugh, Jonathan Chang, Catherine G. Wong, Alain J. Martin, K.S. Ko, Benjamin N. Lee, P. Prakash, Mika Nyström, Eino-Ville Talvala
Publikováno v:
ASYNC
We describe the Lutonium, an asynchronous 8051 microcontroller designed for low Et/sup 2/. In 0.18 /spl mu/m CMOS, at nominal 1.8 V, we expect a performance of 0.5 nJ per instruction at 200 MIPS. At 0.5 V, we expect 4 MIPS and 40 pJ/instruction, corr
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::fe616335b85cea89ea3df8b2cde642f5
https://doi.org/10.1109/async.2003.1199162
https://doi.org/10.1109/async.2003.1199162
Autor:
Tak Kwan Lee, Paul I. Pénzes, Andrew M. Lines, Alain J. Martin, R. Southworth, Uri Cummings, Rajit Manohar, Mika Nyström
Publikováno v:
ARVLSI
The design of an asynchronous clone of a MIPS R3000 microprocessor is presented. In 0.6 /spl mu/m CMOS, we expect performance close to 280 MIPS, for a power consumption of 7 W. The paper describes the structure of a high-performance asynchronous pipe
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::29851b3c1c3c69e91f41bd4798bfdaa2
https://doi.org/10.1109/arvlsi.1997.634853
https://doi.org/10.1109/arvlsi.1997.634853
Publikováno v:
ARVLSI
The presence of precise exceptions in a processor leads to complications in its design. Some recent processor architectures have sacrificed this requirement for performance reasons at the cost of software complexity. We present an implementation stra
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::445c94c03796e41ef8c369c7dad65cdf
https://doi.org/10.1109/arvlsi.2001.915547
https://doi.org/10.1109/arvlsi.2001.915547
Publikováno v:
Power Aware Computing ISBN: 9781441933829
We investigate an efficiency metric for VLSI computation that includes energy. E, and time, t, in the form Et2. We apply the metric to CMOS circuits operating outside velocity saturation when energy and delay can be exchanged by adjusting the supply
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::e30eac05569afd18fd6fdbbcf53cfd9a
https://doi.org/10.1007/978-1-4757-6217-4_15
https://doi.org/10.1007/978-1-4757-6217-4_15