Design and verification of pipelined circuits with Timed Petri Nets

Autor: Rémi Parrot, Mikaël Briday, Olivier H. Roux

Publikováno v: Discrete Event Dynamic Systems
Discrete Event Dynamic Systems, 2023, 33, ⟨10.1007/s10626-022-00371-7⟩

International audience; A fundamental step in circuit design is the placement of pipeline stages, which can drastically increase the data throughput. Retiming allows optimizing the pipeline with regard to a criterion, for example the required number

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_dedup___::029ec32eee91fba3263c3f22dc8eb288
https://hal.science/hal-03952519

Energy Efficiency is Not Enough:Towards a Batteryless Internet of Sounds

Autor: Sébastien Faucou, Mikaël Briday, Vincent Lostanlen, Mathieu Lagrange, Antoine Bernabeu, Jean-Luc Béchennec

Publikováno v: Audio Mostly Conference

This position paper advocates for digital sobriety in the design and usage of wireless acoustic sensors. As of today, these devices all rely on batteries, which are either recharged by a human operator or via solar panels. Yet, batteries contain chem

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::4af3009bfd96e6208108ab52645e1e95
https://doi.org/10.1145/3478384.3478408

Timed Petri Nets with Reset for Pipelined Synchronous Circuit Design

Autor: Olivier Roux, Mikaël Briday, Rémi Parrot

Publikováno v: Application and Theory of Petri Nets and Concurrency
42nd International Conference on Application and Theory of Petri Nets and Concurrency
42nd International Conference on Application and Theory of Petri Nets and Concurrency, Jun 2021, Paris, France. pp.55-75, ⟨10.1007/978-3-030-76983-3_4⟩
Application and Theory of Petri Nets and Concurrency ISBN: 9783030769826
Petri Nets

International audience; This paper introduces an extension of Timed Petri Nets for the modeling of synchronous electronic circuits, addressing pipeline design problems. Petri Nets have been widely used for the modeling of electronic circuits. In part

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_dedup___::06d8dd580bf5a190e0bee1b2bd34a7c7
https://hal.archives-ouvertes.fr/hal-03266806

Hardware Runtime Verification of a RTOS Kernel: Evaluation Using Fault Injection

Autor: Sébastien Pillement, Sébastien Faucou, Dimitry Solet, Mikaël Briday, Jean-Luc Béchennec

Publikováno v: EDCC
14th European Dependable Computing Conference (EDCC)
14th European Dependable Computing Conference (EDCC), Sep 2018, Iasi, Romania. ⟨10.1109/edcc.2018.00016⟩

Nowadays complete systems can be built on a System-on-a-Programmable-Chip that integrates a microcontroller and a FPGA fabric into a single chip. Beside its traditional use to implement hardware accelerators, the FPGA can be used to monitor the softw

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_dedup___::438381ef3a31037858f4c58b9747e343
https://doi.org/10.1109/edcc.2018.00016

ReTiS: a real-time simulation platform. Analysis of real-time applications

Autor: Mikaël Briday, Jean-Luc Bechennec, Yvon Trinquet

Publikováno v: Journal Européen des Systèmes Automatisés. 40:819-846

This paper presents ReTiS, a simulation tool for distributed real-time application analysis. Simulation concerns the operational architecture and takes into account the software (executable code of real-time tasks and real-time operating system) and

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::8ae61040db1d0f0a046ced9aaec85ebc
https://doi.org/10.3166/jesa.40.819-846