Zobrazeno 1 - 10
of 19
pro vyhledávání: '"Michio Yotsuyanagi"'
Autor:
Norihito Kato, Toshio Ohkido, Yuji Nakajima, Tetsuya Matsumoto, Akemi Sakaguchi, Michio Yotsuyanagi
Publikováno v:
IEEE Journal of Solid-State Circuits. 45:707-718
We have developed a 6b 2.7 GS/s folding ADC with on-chip background self-calibration in 90 nm CMOS technology. The ADC achieves high-speed operation of 2.7 GS/s at low power consumption of 50 mW from a 1.0 V power supply and the figure of merit (FOM)
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::681ca9cd623ee52dfc897fde5177f7f5
https://doi.org/10.1109/jssc.2010.2042249
https://doi.org/10.1109/jssc.2010.2042249
Autor:
Fuyuki Okamoto, Yuki Fujimoto, Masayuki Furumiya, Keisuke Hatano, Yasutaka Nakashiba, Michio Yotsuyanagi
Publikováno v:
Electronics and Communications in Japan (Part II: Electronics). 84:28-35
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::c8df65f0922561b48bb45973b88e4921
https://doi.org/10.1002/ecjb.1055.abs
https://doi.org/10.1002/ecjb.1055.abs
Publikováno v:
International Journal of High Speed Electronics and Systems. 11:1-33
This paper briefly reviews recent research on CMOS gigahertz-rate communication circuits and design innovations for overcoming device performance limitations. A multi-channel transmitter and receiver chip set operating at 5 Gb/s has been developed us
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::0e47c0473e4328b50af42060876aa144
https://doi.org/10.1142/s0129156401000770
https://doi.org/10.1142/s0129156401000770
Autor:
Hiroshi Hayama, H. Heiuchi, Michio Yotsuyanagi, Kazuyuki Nakamura, Muneo Fukaishi, H. Ikeno, Y. Hirota, Y. Nakazawa
Publikováno v:
IEEE Journal of Solid-State Circuits. 35:1611-1618
The digital display interface for an ultra-high resolution flat panel (3200/spl times/2400-pixels) requires 16 Gb/s bandwidth; moreover, 20 Gb/s is required when using an 8B10B encoder to increase serial data transmission accuracy. Low power consumpt
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::9d26caede3aed2b05b73e20ea4db5f8f
https://doi.org/10.1109/4.881206
https://doi.org/10.1109/4.881206
Publikováno v:
Analog Integrated Circuits and Signal Processing. 25:227-234
A 1.5 V 8 mW BiCMOS video A/D converter has been developed by using a BiCMOS pumping comparator. Combining Bipolar high-speed and good-matching characteristics with CMOS switched capacitor techniques, this A/D converter is suitable for use in battery
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::a1f79e1e13203158b46c76cda29ffcd6
https://doi.org/10.1023/a:1008365511880
https://doi.org/10.1023/a:1008365511880
Autor:
Norihito Kato, Hiroko Masuda, Kenji Shimomaki, Akemi Sakaguchi, Michio Yotsuyanagi, Takahiro Miki, Toshio Ohkido, Yuji Nakajima, Chikahiro Shiroma
Publikováno v:
CICC
A 7b 1.4 GS/s flash ADC is developed in 45 nm CMOS. This is the first paper of an ADC with offset drift suppression techniques for dynamic comparator and preamplifier. These techniques make the ADC robust against environmental variation. As a result,
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::3a61b2d8fe35c2b522987fc216cdd1c7
https://doi.org/10.1109/cicc.2012.6330608
https://doi.org/10.1109/cicc.2012.6330608
Autor:
Yuki Fujimoto, Tsuyoshi Nagata, Michio Yotsuyanagi, Y. Nakashiba, K. Hatano, Fuyuki Okamoto, Masayuki Furumiya
Publikováno v:
1999 Symposium on VLSI Circuits. Digest of Papers (IEEE Cat. No.99CH36326).
A CMOS imager with new focal-plane motion detectors has been developed as the front-end of vision systems. The chip generates both a normal video signal and a local image signal; i.e. the local area where the motion is detected is automatically scann
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::f1aa34c658867ff40b76db310edcb958
https://doi.org/10.1109/vlsic.1999.797264
https://doi.org/10.1109/vlsic.1999.797264
Publikováno v:
1998 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.98CH36215).
We developed a new phase detector which can perform 1:2 data demultiplexing function. A newly developed pulse compensation technique enables one to output the analog phase difference for a half-frequency clock. This circuit can be used as both a phas
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::9c3c2efb8b347428dc71a81df562bc3e
https://doi.org/10.1109/vlsic.1998.688081
https://doi.org/10.1109/vlsic.1998.688081
Publikováno v:
2000 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.00CH37103).
The authors report a duty cycle repeater (DCR) which obtains 50% duty-cycle complementary clock signals from a wide range of input duty-cycle signals from 30% to 70%, even when input signals suffer from timing skew. It features a simple CMOS structur
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::934ccd8a6e0e12bc19c94c5b81f40480
https://doi.org/10.1109/vlsic.2000.852847
https://doi.org/10.1109/vlsic.2000.852847
