Zobrazeno 1 - 9
of 9
pro vyhledávání: '"Michel J. Abou-Khalil"'
Autor:
Venkata Narayana Rao Vanukuru, Steven M. Shank, Anthony K. Stamper, Balaji Swaminathan, Aaron L. Vallett, Alvin J. Joseph, Rick Phelps, John J. Ellis-Monaghan, Adusumilli Siva P, Mark D. Jaffe, Ananth Sundaram, Michel J. Abou-Khalil, Randy L. Wolf
Publikováno v:
2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S).
Integration of high performance switch with Low Noise Amplifier (LNA) devices results in state of the art performance for 5G Front End Module applications. Here we review switch+ LNA performance metrics and its evolution over the last 10 years and hi
Autor:
Kai Esmark, C. Seguin, Christian Russ, Kiran V. Chatty, Michel J. Abou-Khalil, Junjun Li, Robert J. Gauthier, R. Halbach, David Alvarez
Publikováno v:
Microelectronics Reliability. 49:1417-1423
Decrease of the drain silicide-blocking-to-gate spacing in gate-silicided-ESD-NMOSFETs improves the TLP and HBM failure levels up to 30%, while no effect is observed when decreasing the source silicide-blocking-to-gate spacing. Failure analysis and s
Autor:
John J. Ellis-Monaghan, James A. Slinkman, Michel J. Abou-Khalil, Steven M. Shank, Richard A. Phelps, Zhong-Xiang He, Jeff Gross, Jeffrey P. Gambino, Mark D. Jaffe, Randy L. Wolf, Alan B. Botula, Alvin J. Joseph
Publikováno v:
2015 IEEE 15th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems.
Over the past few years, CMOS Silicon-oninsulator (SOI) has emerged as the dominant technology for RF switches in RF front end modules for cell phones and WiFi. RF SOI technologies were created from silicon processes originally used for high speed lo
Autor:
Robert J. Gauthier, Kiran V. Chatty, Christian Russ, D. Kontos, Junjun Li, C. Seguin, Michel J. Abou-Khalil, David Alvarez, R. Halbach
Publikováno v:
Microelectronics Reliability. 46:1597-1602
Electrical and SEM analysis of gate-silicided (GS) ESD NMOSFETs in a 65nm bulk CMOS technology show that the failure mechanism changes from source-to-drain filamentation to drain-to-substrate short when a p-type ESD implant (ED) is used. Simulations
Autor:
Mark D. Jaffe, Alan B. Botula, Randy L. Wolf, Steven Moss, James A. Slinkman, Michel J. Abou-Khalil, John J. Ellis-Monaghan, Alvin J. Joseph, Rick Phelps
Publikováno v:
2013 IEEE Radio Frequency Integrated Circuits Symposium (RFIC).
In this study, we define and investigate the maximum power handling capability (Pmax) in an SOI RF shunt branch switch. One of the critical factor in the Pmax is the non-uniform voltage division across an OFF shunt branch. In this study we provide a
Autor:
Alvin J. Joseph, Theodore J. Letavic, James A. Slinkman, Michel J. Abou-Khalil, Mark D. Jaffe, Alan B. Botula
Publikováno v:
2013 25th International Symposium on Power Semiconductor Devices & IC's (ISPSD).
We present a new device design for 20V application in thin body SOI technology. High breakdown voltage is achieved by forming RX-bound field plates which deplete the drift region of an LDMOS structure using only lateral electric field coupling. A bas
Autor:
C. Russ, Kiran V. Chatty, C. Seguin, David Alvarez, Michel J. Abou-Khalil, Junjun Li, K. Esmark, R. Halbach, Robert J. Gauthier
Publikováno v:
2007 29th Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD).
Decrease of the drain silicide-blocking-to-gate spacing in gate-silicided-ESD-NMOSFETs improves the TLP and HBM failure levels up to 30%, while no effect is observed when decreasing the source silicide-blocking-to-gate spacing. Failure analysis and s
Autor:
Kiran V. Chatty, David Alvarez, C. Russ, Robert J. Gauthier, B.J. Kwon, Michel J. Abou-Khalil
Publikováno v:
2007 29th Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD).
Process and design optimization of NMOSFETs with ESD implant is presented. A 2 V reduction in trigger voltage, a 30% higher failure current, 50% reduction in on-resistance is achieved with a 13X increase in leakage current for a 2.5 V NMOSFET. Self-p
Autor:
David Alvarez, Jing Li, Kiran V. Chatty, C. Russ, R. Halbach, Robert J. Gauthier, C. Seguin, Michel J. Abou-Khalil
Publikováno v:
13th International Symposium on the Physical and Failure Analysis of Integrated Circuits.
Electrical and SEM analysis of gate-silicided (GS) and gate-non-silicided (GNS) ESD NMOSFETs in a 65nm bulk CMOS technology show that the failure mechanism switches away from classical drain-to-source filamentation when the silicidation between the s