ECC Memory for Fault Tolerant RISC-V Processors

Autor: Dörflinger, Alexander, Guan, Yejun, Michalik, Sören, Michalik, Sönke, Naghmouchi, Jamin, Michalik, Harald

Publikováno v: Brinkmann A., Karl W., Lankes S., Tomforde S., Pionteck T., Trinitis C. (eds), Architecture of Computing Systems – ARCS 2020. ARCS 2020. Lecture Notes in Computer Science, vol 12155, Page 44-55, Springer, Cham. https://doi.org/10.1007/978-3-030-52794-5_4--Lecture Notes in Computer Science--Lect. Notes Comput. Sci.--0302-9743
Architecture of Computing Systems – ARCS 2020

Numerous processor cores based on the popular RISC-V Instruction Set Architecture have been developed in the past few years and are freely available. The same applies for RISC-V ecosystems that allow to implement System-on-Chips with RISC-V processor

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_dedup___::c9dc1856caa9a86534bdd31daa679059
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