Zobrazeno 1 - 10
of 10
pro vyhledávání: '"Michal Rimon"'
Publikováno v:
IEEE Design & Test of Computers. 21:84-93
Functional verification is widely recognized as the bottleneck of the hardware design cycle. With the ever-growing demand for greater performance and faster time to market, coupled with the exponential growth in hardware size, verification has become
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::affbe072574cd5b7c952e0f8f428f12c
https://doi.org/10.1109/mdt.2004.1277900
https://doi.org/10.1109/mdt.2004.1277900
Publikováno v:
Hardware and Software: Verification and Testing ISBN: 9783642396106
Haifa Verification Conference
Haifa Verification Conference
The ever-growing microarchitecture complexity of processors creates a widening gap between the verification plan and the test generation technologies used in its implementation. This gap impacts the cost and quality of the verification process. To ov
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::9184bd663491ca0010a0f0fc5b304954
https://doi.org/10.1007/978-3-642-39611-3_17
https://doi.org/10.1007/978-3-642-39611-3_17
Publikováno v:
Automated Software Engineering. 1:79-128
Over the past 30 years, scientific software models have played an increasingly prominent role in the conduct of science. Unfortunately, scientific models can be difficult and time-consuming to implement, and there is little software engineering suppo
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::30ab4db365b00906521436709542aad0
https://doi.org/10.1007/bf00871693
https://doi.org/10.1007/bf00871693
Publikováno v:
DAC
Microarchitectural information regarding various aspects of instruction execution can help processor-level stimuli generators more easily reach verification goals. While many such aspects are based on common microarchitectural concepts, their specifi
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::ed9fadb4810ea6270831ebefcde1958d
https://doi.org/10.1145/2024724.2024914
https://doi.org/10.1145/2024724.2024914
Publikováno v:
Hardware and Software: Verification and Testing ISBN: 9783642195822
Haifa Verification Conference
Haifa Verification Conference
Many modern microprocessor architectures utilize simultaneous multithreading (SMT) for increased performance. This trend is exemplified in IBM's Power series of high-end microprocessors which steadily increased the number of threads in a system in it
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::06e56517d790ffd6e6900de6cc82be35
https://doi.org/10.1007/978-3-642-19583-9_15
https://doi.org/10.1007/978-3-642-19583-9_15
Autor:
Leitner Lawrence, S. M. German, Jackson Jonathan, Fady Copty, Richard D. Peterson, Schumann John A, Randall R. Pratt, Michal Rimon, Johannes Koesters, Amir Nahir, Klaus-Dieter Schubert, Holger Horbach, Bishop Brock, Oz Hershkovitz, Jörg Behrend, John M. Ludden, G. B. Meil, Charles Meissner, S. Ayub, Ronny Morad, Klaus Keuerleber, Viresh Paruthi
Publikováno v:
IBM Journal of Research and Development. 59:11:1-11:17
This paper describes methods and techniques used to verify the POWER8™ microprocessor. The base concepts for the functional verification are those that have been already used in POWER7® processor verification. However, the POWER8 design point prov
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::2fc3f43b8e07be8e4ab9fa6ece84a2a2
https://doi.org/10.1147/jrd.2014.2380271
https://doi.org/10.1147/jrd.2014.2380271
Autor:
Yossi Lichtenstein, Michael Vinov, Itai Jaeger, S. Johnson, Allon Adir, D. Jani, Michal Rimon
Publikováno v:
HLDVT
Having only recently entered the mainstream, configurable processor technology already provides practical automated hardware design. In this paper, we address the challenges of verifying these software-constructed hardware artifacts and show that sop
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::664de27182085a0decd2256349add261
https://doi.org/10.1109/hldvt.2006.319970
https://doi.org/10.1109/hldvt.2006.319970
Autor:
Y. Arbetman, Y. Liechtenstein, Allon Adir, Michal Rimon, Bella Dubrov, Michael Vinov, A. Cofler, M.A. Calligaro, G. Duffy
Publikováno v:
DAC
Parallelism in processor architecture and design imposes a verification challenge as the exponential growth in the number of execution combinations becomes unwieldy. In this paper we report on the verification of a very large instruction word process
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::c86491dd10d787854634441489651321
https://doi.org/10.1109/dac.2005.193921
https://doi.org/10.1109/dac.2005.193921
Publikováno v:
DAC
We report on our experience with a new test generation language for processor verification. The verification of two superscalar multiprocessors is described and we show the ease of expressing complex verification tasks. The cost and benefit are demon
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::4f0457de2ab045919debb0692768f698
https://doi.org/10.1145/996566.996578
https://doi.org/10.1145/996566.996578
Publikováno v:
HLDVT
Test program generation typically involves the resolution of constraints to make the tests legal and interesting for verification. This is often achieved through the values of resources used by the instructions in the test. The difficulty is that the
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::9f2846f7602890e291c48f3a11c6ebd1
https://doi.org/10.1109/hldvt.2001.972809
https://doi.org/10.1109/hldvt.2001.972809