Zobrazeno 1 - 10
of 10
pro vyhledávání: '"Michael Zelikson"'
Autor:
Nicolas Butzen, Harish Krishnarnurthy, Zakir Ahmed, Sheldon Weng, Krishnan Ravichandran, Michael Zelikson, James Tschanz, Jonathan Douglas
Publikováno v:
2023 IEEE International Solid- State Circuits Conference (ISSCC).
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::db39fee4cfaf9f5b42ef0dcbe759ed39
https://doi.org/10.1109/isscc42615.2023.10067583
https://doi.org/10.1109/isscc42615.2023.10067583
Autor:
Michael Zelikson, Kosta Luria, Lior Gil, Yuval Brown, Vadim Goldenbeg, Dor Kasif, Elias Hlees, Alex Vinichuk
Publikováno v:
2023 IEEE International Solid- State Circuits Conference (ISSCC).
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::e0605b5c12212fb7d5b9ab9405ef3e09
https://doi.org/10.1109/isscc42615.2023.10067368
https://doi.org/10.1109/isscc42615.2023.10067368
Publikováno v:
IEEE Journal of Solid-State Circuits. 51:752-762
A dual-mode digital power gate (PG) and linear low-drop-out regulator (LDO) has been demonstrated in 14 nm. A modified flipped source follower driver circuit is used to minimize dI / dt droops. The LDO has a novel compensation method which utilizes c
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::87f5eacc25387ffab6881e219bbb5073
https://doi.org/10.1109/jssc.2015.2512387
https://doi.org/10.1109/jssc.2015.2512387
Autor:
Muhammad Abozaed, Eyal Fayneh, Ernest Knoll, Michael Zelikson, Yair Talker, Marcelo Yuffe, Saher Abu Rahme, Ziv Shmuely
Publikováno v:
ISSCC
Intel's 6th generation Core processor (code named “Skylake” or SKL) was designed to enable PC performance and user-experience at smaller and thinner form factors and enable fan-less PC platforms. It required optimization to an extremely low therm
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::3ffef104629d97be7aaa5e39e73e2390
https://doi.org/10.1109/isscc.2016.7417912
https://doi.org/10.1109/isscc.2016.7417912
Autor:
Tsvika Kurts, Michael Zelikson, Kosta Luria, Marcelo Yuffe, Moty Mehalel, Ernest Knoll, E. Altshuler, Joseph Shor, Eyal Fayneh
Publikováno v:
IEEE Journal of Solid-State Circuits. 47:194-205
This paper describes the second-generation Intel Core processor, a 32-nm monolithic die integrating four IA cores, a processor graphics, and a memory controller. Special attention is given to the circuit design challenges associated with this kind of
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::476f895019ff0c08cc33b01dfec728e7
https://doi.org/10.1109/jssc.2011.2167814
https://doi.org/10.1109/jssc.2011.2167814
Publikováno v:
ISSCC
In recent generations of microprocessors, there has been an increase in the number and types of processors integrated on the same die. For example, in [1] several IA (Intel architecture) cores have been integrated on-chip with a graphics processor. M
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::41923965f8722df9c15a4f42b33a65be
https://doi.org/10.1109/isscc.2015.7062973
https://doi.org/10.1109/isscc.2015.7062973
Publikováno v:
ICECS
An analytic method to evaluate frequency dependent losses in on-chip DC-DC buck converters is presented in this paper. Microprocessors or chipsets exhibit wide dynamic range of load current varying from 50mA up to 1.5 A per phase at full operation. P
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::d05c02ed0f77fd7bda4b63773c339807
https://doi.org/10.1109/icecs.2010.5724735
https://doi.org/10.1109/icecs.2010.5724735
Publikováno v:
2010 IEEE 26-th Convention of Electrical and Electronics Engineers in Israel.
An analytic method to evaluate frequency dependent losses in on-chip DC-DC buck converters is presented in this paper. These converters feature high switching losses caused by the skin effect in the package inductors. The frequency dependent air-core
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::3443fc37250c97855d7707e2a6c26ead
https://doi.org/10.1109/eeei.2010.5662132
https://doi.org/10.1109/eeei.2010.5662132
Autor:
J. Park, Betty Livshitz, C. Dickey, A. Sherman, Robert A. Groves, Alon Amir, A. Barger, Y. Tretiakov, Raminderpal Singh, David L. Harame, Israel A. Wagner, Michael Zelikson, Donald L. Jordan, Sue E. Strang, David Goren, Rachel Gordin
Publikováno v:
DAC
This paper expands the on-chip interconnect-aware methodology for high-speed analog and mixed signal design, presented in D. Goren et al. (2002), into a wider class of designs, including dense layout CMOS design. The proposed solution employs a set o
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::cb5b313048c6b90654ca5f4c75851b72
https://doi.org/10.1145/775832.776017
https://doi.org/10.1145/775832.776017
Publikováno v:
Proceedings: 6th IEEE Workshop on Signal Propagation on Interconnects.
In this paper, we present a generic procedure for creating accurate and efficient expressions for calculating the low frequency inductance of on-chip transmission lines. The modeling of the inductance is an integral part of interconnect-aware A&MS de
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::324073f1dacfdd6f3b8139a9a6d1b252
https://doi.org/10.1109/spi.2002.258319
https://doi.org/10.1109/spi.2002.258319