Zobrazeno 1 - 10
of 26
pro vyhledávání: '"Michael Stephen Floyd"'
Autor:
Pradip Bose, William J. Starke, Christian Zoellin, Ramon Bertran, Satish Kumar Sadasivam, Alper Buyuktosunoglu, Silvia M. Müller, Matthias Pflanz, Robert K. Montoye, Michael Normand Goulet, John-David Wellman, Nagu Dhanwada, Dung Q. Nguyen, Marcy E. Byers, José E. Moreira, Balaram Sinharoy, Richard J. Eickemeyer, Christopher Gonzalez, Thompto Brian W, Andreas Wagner, Karthik Swaminathan, Hans M. Jacobson, Nandhini Chandramoorthy, Michael Stephen Floyd, Jeffrey A. Stuecheli, Rahul M. Rao
Publikováno v:
ISCA
We present the novel micro-architectural features, supported by an innovative and novel pre-silicon methodology in the design of POWER10. The resulting projected energy efficiency boost over POWER9 is 2.6x at core level (for SPECint) and up to 3x at
Autor:
David Hogenmiller, Pierce Chuang, Saiful Islam, Ricardo Escobar, Daniel Lewis, Joshua Friedrich, Donald W. Plass, Rahul M. Rao, Pawel Owczarczyk, Paul H. Muench, Eric Fluhr, Michael A. Sperling, Juergen Pille, Vinod Ramadurai, Jose Angel Paredes, Michael Stephen Floyd, Christopher Gonzalez, Phillip J. Restle, Timothy Diemoz, Ryan Nett, Christos Vezyrtis, Ryan Kruse, Daniel M. Dreps
Publikováno v:
IEEE Journal of Solid-State Circuits. 53:91-101
The POWER9TM family of chips is fabricated in 14-nm silicon-on-insulator finFET technology using 17 levels of copper interconnect. The 695-mm2 24-core microprocessor features a new core based on an execution slice microarchitecture. The chip contains
Autor:
David T. Hui, Pierce I-Jen Chuang, Eickhoff Susan M, Alper Buyuktosunoglu, Phillip J. Restle, Michael Stephen Floyd, Richard F. Rizzolo, Preetham M. Lobo, S. Carey, Tobias Webel, Christos Vezyrtzis, Ramon Bertran, Gerard M. Salem, Thomas Strach, Pawel Owczarczyk, Stelios G. Tsapepas
Publikováno v:
ISSCC
Enterprise server processor designs, which operate at extreme high frequencies and power envelopes, depend critically on power supply noise mitigation techniques. With supply voltage scaling, very high current draws, and broad usage of clock gating,
Autor:
Eric Fluhr, Vinod Ramadurai, Michael Stephen Floyd, Daniel M. Dreps, Rahul M. Rao, Saiful Islam, Michael A. Sperling, Christopher Gonzalez, David Hogenmiller, Juergen Pille, Jose Angel Paredes, Donald W. Plass, Ryan Nett, Ryan Kruse
Publikováno v:
ISSCC
Cognitive computing and cloud infrastructure require flexible, connectable, and scalable processors with extreme IO bandwidth. With 4 distinct chip configurations, the POWER9 family of chips delivers multiple options for memory ports, core thread cou
Autor:
Michael Stephen Floyd, Alper Buyuktosunoglu, Phillip J. Restle, Richard F. Rizzolo, Gerard M. Salem, Preetham M. Lobo, Thomas Strach, Divya Pathak, Pierce I-Jen Chuang, S. Carey, Otto Torreiter, Christos Vezyrtzis, Malcolm Scott Ware, Ramon Bertran, Tobias Webel
Publikováno v:
ISSCC
Successful power supply noise mitigation requires a system-level approach that includes design and modeling of the mitigation circuits with the power delivery network (PDN) on the chip, the chip module, the backplane, and the voltage regulator module
Autor:
Pawel Owczarczyk, Michael A. Sperling, Pierce Chuang, Phillip J. Restle, Joshua Friedrich, Christos Vezyrtzis, Timothy Diemoz, Paul H. Muench, Eric Fluhr, Michael Stephen Floyd
Publikováno v:
ISSCC
Increasing transistor counts in modern processors can create instantaneous changes in current, driving nanosecond-speed supply voltage (V DD ) droops that require extra guardband for correct product operation. The POWER9 processor uses an adaptive cl
Autor:
John B. Carter, Alan J. Drake, Michael Stephen Floyd, Bishop Brock, Malcolm S. Allen-Ware, Charles R. Lefurgy, Robert W. Berry, Jose A. Tierno
Publikováno v:
IEEE Micro. 33:35-45
Microprocessor voltage levels traditionally include substantial margin to ensure reliable operation despite variations in manufacturing, workload, and environmental parameters. This margin allows the microprocessor to function correctly during worst-
Autor:
Jingwen Leng, Matthew Halpern, Yazhou Zu, Charles R. Lefurgy, Michael Stephen Floyd, Vijay Janapa Reddi
Publikováno v:
MICRO
The traditional guardbanding approach to ensure processor reliability is becoming obsolete because it always over-provisions voltage and wastes a lot of energy. As a next-generation alternative, adaptive guardbanding dynamically adjusts chip clock fr
Autor:
Bulent Abali, B. C. Drerup, Bartholomew Blaner, F. A. Campisano, R. B. Leavens, Ronald Nick Kalla, Derek Edward Williams, E. N. Lais, S. M. Willenborg, Michael Stephen Floyd, Guy Lynn Guthrie, Charles F. Marino, L. B. Arimilli
Publikováno v:
IBM Journal of Research and Development. 62:1:1-1:11
IBM POWER9 is a family of processor chips designed to serve a diverse set of workloads. New features have been added to POWER9 to address emerging workloads such as cognitive and artificial intelligence applications. POWER9 also further enhances feat
Publikováno v:
IEEE Micro. 30:7-15
The Power7 is IBM's first eight-core processor, with each core capable of four-way simultaneous-multithreading operation. Its key architectural features include an advanced memory hierarchy with three levels of on-chip cache; embedded-DRAM devices us