Zobrazeno 1 - 10
of 172
pro vyhledávání: '"Michael Nicolaidis"'
Publikováno v:
IEEE Transactions on Sustainable Computing. 6:493-506
Silicon-based CMOS technologies are fast approaching their ultimate limits. By approaching these limits, fabrication yield, reliability, and power densities, worsen steadily making further nanometric scaling increasingly difficult. These problems wou
Publikováno v:
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 39:464-477
In modern SoCs embedded memories should be protected by ECC against field failures to achieve acceptable reliability. They should also be repaired after fabrication to achieve acceptable fabrication yield, as well as during lifetime to increase lifes
Publikováno v:
IEEE 26th International Symposium on
Testing and Robust System Design (IOLTS)
Testing and Robust System Design (IOLTS), Jul 2020, Napoli, Italy. pp.1-6, ⟨10.1109/IOLTS50870.2020.9159731⟩
IOLTS
IOLTS 2020-IEEE 26th International Symposium on
Testing and Robust System Design
Testing and Robust System Design, Jul 2020, Napoli, Italy. pp.1-6, ⟨10.1109/IOLTS50870.2020.9159731⟩
Testing and Robust System Design (IOLTS)
Testing and Robust System Design (IOLTS), Jul 2020, Napoli, Italy. pp.1-6, ⟨10.1109/IOLTS50870.2020.9159731⟩
IOLTS
IOLTS 2020-IEEE 26th International Symposium on
Testing and Robust System Design
Testing and Robust System Design, Jul 2020, Napoli, Italy. pp.1-6, ⟨10.1109/IOLTS50870.2020.9159731⟩
International audience; Memory system reliability is a serious concern in many systems today and is becoming more worrisome as technology scales, system size grows and the demand of aggressive voltage reduction becomes more stringent. Thus, disposing
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::cdb130d892c1cbe86e92a35e6a27fb82
https://hal-lirmm.ccsd.cnrs.fr/lirmm-03035798/document
https://hal-lirmm.ccsd.cnrs.fr/lirmm-03035798/document
Publikováno v:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, IEEE, 2018, 26 (8), pp.1438-1451. ⟨10.1109/TVLSI.2018.2818021⟩
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, IEEE, 2018, 26 (8), pp.1438-1451. ⟨10.1109/TVLSI.2018.2818021⟩
International audience; In nanometer technologies, circuits are more and more sensitive to various kinds of perturbations. Alpha particles and atmospheric neutrons induce single-event upsets, affecting memory cells, latches, and flip-flops. They also
Publikováno v:
ieee, 19-Issue 1, pp.3-5, 2019, IEEE Transactions on Device and Materials Reliability
You are reading the Editorial of the Special Section of IEEE Transactions on Device and Materials Reliability (TDMR) with a collection of the best papers of the 2018 edition of the IEEE International On-Line Testing 50 and Robust System Design Sympos
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::1ae6d439dee955092d519370960eea6d
https://hal.archives-ouvertes.fr/hal-02080501
https://hal.archives-ouvertes.fr/hal-02080501
Publikováno v:
Design, Automation & Test in Europe (DATE'2018)
Design, Automation & Test in Europe (DATE'2018), Mar 2018, Dresden, Germany
DATE
Design, Automation & Test in Europe (DATE'2018), Mar 2018, Dresden, Germany
DATE
International audience; The double sampling paradigm is an efficient method to protect the circuits against soft-errors. But the data that are going out of the area protected by double sampling are still vulnerable. In this paper we proposed an archi
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::6a827eb6682b2745facc17082e8e3f19
https://hal.archives-ouvertes.fr/hal-01806232
https://hal.archives-ouvertes.fr/hal-01806232
Publikováno v:
22th IEEE European Test Symposium (ETS'17)
22th IEEE European Test Symposium (ETS'17), May 2017, Limassol, Cyprus. pp.1-6
ETS
22th IEEE European Test Symposium (ETS'17), May 2017, Limassol, Cyprus. pp.1-6
ETS
International audience; 3D integration opens up new opportunities for future multiprocessor chips by enabling fast and highly scalable 3D Network-on-Chip (NoC) topologies. However, in an aim to reduce the cost of Through-silicon via (TSV), partially
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::960cd176397d57c351b268b564972f60
https://hal.archives-ouvertes.fr/hal-01523897
https://hal.archives-ouvertes.fr/hal-01523897
Publikováno v:
IEEE Latin-American Test Symposium (LATS 2017)
IEEE Latin-American Test Symposium (LATS 2017), Mar 2017, Bogota, Colombia. pp.1-4
LATS
IEEE Latin-American Test Symposium (LATS 2017), Mar 2017, Bogota, Colombia. pp.1-4
LATS
International audience; With NoCs (Networks-on-Chips) becoming a central part of today’s many-core systems, ensuring a good level of performance at the routing level has never been so crucial. In previous works, we have introduced a novel method fo
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::a9dc686bdc37d52971ec409ffebce700
https://hal.archives-ouvertes.fr/hal-01523899
https://hal.archives-ouvertes.fr/hal-01523899
Publikováno v:
IEEE International Symposium on Circuits and Systems (LASCAS 2017)
IEEE International Symposium on Circuits and Systems (LASCAS 2017), Feb 2017, Bariloche, Argentina. pp.1-4
LASCAS
IEEE International Symposium on Circuits and Systems (LASCAS 2017), Feb 2017, Bariloche, Argentina. pp.1-4
LASCAS
International audience; In nanometer technologies, circuits are more and more sensitive to various kinds of perturbations. Alpha particles and atmospheric neutrons are affecting storage elements as well as the combinational logic. In the past, the ma
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::35e8c4629e79b68965a5751c3bb18dd2
https://hal.archives-ouvertes.fr/hal-01523903
https://hal.archives-ouvertes.fr/hal-01523903
Publikováno v:
ASP-DAC
ACM/IEEE Design Automation Conference (ASPDAC 2017)
ACM/IEEE Design Automation Conference (ASPDAC 2017), Jan 2017, Chiba/Tokyo, Japan. pp.672-677
ACM/IEEE Design Automation Conference (ASPDAC 2017)
ACM/IEEE Design Automation Conference (ASPDAC 2017), Jan 2017, Chiba/Tokyo, Japan. pp.672-677
International audience; As the number of processing elements in modern chips keeps increasing, the evaluation of new designs will need to account for various challenges at the NoC level. To cope with the impractically long run times when simulating l
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::00c6edf23e9c3c8f94d2d0e8c9a73d0b
https://hal.archives-ouvertes.fr/hal-01523898
https://hal.archives-ouvertes.fr/hal-01523898