Zobrazeno 1 - 10
of 11
pro vyhledávání: '"Michael Muehlberghuber"'
Autor:
Frank K. Gurkaynak, Michael Muehlberghuber, Robert Schilling, Stefan Mangard, Thomas Unterluggauer, Luca Benini
Publikováno v:
2018 Design, Automation & Test in Europe Conference & Exhibition (DATE)
DATE
DATE
Embedded devices in the Internet-of-Things require encryption functionalities to secure their communication. However, side-channel attacks and in particular differential power analysis (DPA) attacks pose a serious threat to cryptographic implementati
Autor:
Stefan Mangard, Thomas Korak, Frank K. Gurkaynak, Luca Benini, Robert Schilling, Michael Muehlberghuber, Thomas Unterluggauer
Publikováno v:
Smart Card Research and Advanced Applications ISBN: 9783319752075
CARDIS
CARDIS
In recent years, many leakage-resilient schemes have been published. These schemes guarantee security against side-channel attacks given bounded leakage of the underlying primitive. However, it is a challenging task to reliably determine these leakag
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::47b2efc98073480b7f9a16f08f001654
http://hdl.handle.net/11585/677255
http://hdl.handle.net/11585/677255
Publikováno v:
Constructive Side-Channel Analysis and Secure Design ISBN: 9783319214757
COSADE
COSADE
We present Zorro, a taped-out ASIC hosting three distinct authenticated encryption architectures based on the SpongeWrap construction. All designs target resource-constrained environments such as smart cards or embedded devices and therefore, have be
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::20bcbe82238c81dd0ea7b75ec06f9bf0
https://doi.org/10.1007/978-3-319-21476-4_15
https://doi.org/10.1007/978-3-319-21476-4_15
Publikováno v:
HOST
The detectability of malicious circuitry on FPGAs with varying placement properties yet has to be investigated. The authors utilize a Xilinx Virtex-II Pro target platform in order to insert a sequential denial-of-service Trojan into an existing AES d
Publikováno v:
HASP@ISCA
We infiltrate the ASIC development chain by inserting a small denial-of-service (DoS) hardware Trojan at the fabrication design phase into an existing VLSI circuit, thereby simulating an adversary at a semiconductor foundry. Both the genuine and the
Publikováno v:
Smart Card Research and Advanced Applications ISBN: 9783642372872
CARDIS
CARDIS
We present GrAEStl, a combined hardware architecture for the Advanced Encryption Standard (AES) and Grostl, one of the final round candidates of the SHA-3 hash competition. GrAEStl has been designed for low-resource devices implementing AES-128 (encr
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::043830ff2685e0243c1b35a87783ef7a
https://doi.org/10.1007/978-3-642-37288-9_12
https://doi.org/10.1007/978-3-642-37288-9_12
Publikováno v:
ICECS
Compressed sensing allows to reconstruct sparse signals sampled at sub-Nyquist rates. However, reconstruction of the original signal requires high computational effort, even for problems of moderate size. Especially for applications with real-time re
Publikováno v:
VLSI-SoC
We propose a block-cipher-based hardware architecture for authenticated encryption (AE) applications supporting the Ethernet standard IEEE 802.3ba. Our main design goal was to achieve high throughput on FPGA platforms. Compared to previous works aimi
Publikováno v:
IFIP Advances in Information and Communication Technology
20th International Conference on Very Large Scale Integration (VLSI-SoC)
20th International Conference on Very Large Scale Integration (VLSI-SoC), Aug 2012, Santa Cruz, CA, United States. pp.1-20, ⟨10.1007/978-3-642-45073-0_1⟩
VLSI-SoC: From Algorithms to Circuits and System-on-Chip Design ISBN: 9783642450723
VLSI-SoC (Selected Papers)
20th International Conference on Very Large Scale Integration (VLSI-SoC)
20th International Conference on Very Large Scale Integration (VLSI-SoC), Aug 2012, Santa Cruz, CA, United States. pp.1-20, ⟨10.1007/978-3-642-45073-0_1⟩
VLSI-SoC: From Algorithms to Circuits and System-on-Chip Design ISBN: 9783642450723
VLSI-SoC (Selected Papers)
International audience; The Advanced Encryption Standard (AES) running in the Galois/Counter Mode of Operation represents a de facto standard in the field of hardware-accelerated, block-cipher-based high-speed authenticated encryption (AE) systems. W
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::202678f714767fc9d9c8dc3b8fe7a8e5
https://hal.inria.fr/hal-01456959
https://hal.inria.fr/hal-01456959
Autor:
Pasquale Davide Schiavone, Robert Schilling, Igor Loi, Germain Haugou, Frank K. Gurkaynak, Luca Benini, Francesco Conti, Davide Rossi, Michael Gautschi, Michael Muehlberghuber, Antonio Pullini, Stefan Mangard
Publikováno v:
IEEE Transactions on Circuits and Systems I: Regular Papers
Near-sensor data analytics is a promising direction for IoT endpoints, as it minimizes energy spent on communication and reduces network load - but it also poses security concerns, as valuable data is stored or sent over the network at various stages