Zobrazeno 1 - 10
of 16
pro vyhledávání: '"Michael Laisne"'
Autor:
Michael Laisne, Alfred Crouch, Michele Portolan, Martin Keim, Hans Martin Von Staudt, Bradford G. Van Treuren, Jeff Rearick, Songlin Zuo
Publikováno v:
2022 IEEE International Test Conference (ITC).
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::c0876c43e15bd73a7dd7331af2be35a6
https://doi.org/10.1109/itc50671.2022.00084
https://doi.org/10.1109/itc50671.2022.00084
Publikováno v:
ITC
IJTAG (IEEE 1687) has proven to successfully address the challenge of test integration for “digital instruments” in digital systems on chip (SoCs). Yet, beyond SoCs, mixed signal IP presents an even bigger obstacle. This is particularly true for
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::4ad34904103821179c3cbf703ba29814
https://doi.org/10.1109/itc44778.2020.9325267
https://doi.org/10.1109/itc44778.2020.9325267
Publikováno v:
Computer. 50:92-95
Despite the success of IEEE 1687, it has one significant shortcoming: it's difficult to use on devices without an 1149.1 test access port controller. IEEE P1687.1 addresses this problem.
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::6094e2450e0cc378c63d2e966bd6940b
https://doi.org/10.1109/mc.2017.186
https://doi.org/10.1109/mc.2017.186
Publikováno v:
ITC
Many analog and mixed signal devices have very few or no digital pins. In spite of this, these products can be highly complex internally, including significant digital content. They may contain various sensors and control circuitry, which react to a
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::f4b5b6fee3827bfbb413b23e667b79ff
https://doi.org/10.1109/test.2017.8242069
https://doi.org/10.1109/test.2017.8242069
Publikováno v:
ISQED
Non-robust tests for path delay faults (PDFs) have gained importance in industry as a high percentage of PDFs are non-robustly testable in comparison to robustly testable PDFs. In this paper we present a novel function-based method to generate test p
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::9ebdfacc2c591738e8e918927fc6d785
https://doi.org/10.1109/isqed.2007.81
https://doi.org/10.1109/isqed.2007.81
Publikováno v:
VLSI Design
This paper presents a novel function-based test generation technique for path delay faults (PDFs) under the launch-off-capture (LOC) scan architecture. The LOC architecture imposes the condition that the second test pattern must be a functional respo
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::a08fc646112d9024a429fea37c986899
https://doi.org/10.1109/vlsid.2007.86
https://doi.org/10.1109/vlsid.2007.86
Autor:
Edward Flanigan, Rajsekhar Adapa, Hailong Cui, Michael Laisne, Spyros Tragoudas, Tsvetomir Petrov
Publikováno v:
20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems (VLSID'07); 2007, p805-812, 8p
Publikováno v:
Computer (00189162); Jul2017, Vol. 50 Issue 7, p92-95, 4p
Autor:
Marinissen, Erik Jan
Publikováno v:
2013 International Symposium onVLSI Design, Automation & Test (VLSI-DAT); 2013, p1-7, 7p
Publikováno v:
20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems (VLSID'07); 2007, pv-xvii, 13p