Zobrazeno 1 - 8
of 8
pro vyhledávání: '"Michael L. Hattendorf"'
Autor:
Benjamin J. Orr, Nathan Jack, C. Auth, A. Schmitz, Tony Acosta, Steven S. Poon, Che-Yun Lin, Abdur Rahman, C. AnDyke, Rahim Kasim, K. Downes, G. McPherson, Sunny Chugh, Madhavan Atul, D. Nminibapiel, Adam Neale, K. Sethi, Seung Hwan Lee, S. Ramey, Tanmoy Pramanik, Michael L. Hattendorf, Emre Armagan, J. Palmer, Subhash M. Joshi, Ian R. Post, C. M. Pelto, P. Nayak, Yeoh Andrew W, G. Martin, Gerald S. Leatherman, H. Wu, N. Seifert, A. Lowrie, R. Grover, H. Mao
Publikováno v:
IRPS
We provide a comprehensive overview of the reliability characteristics of Intel’s 10+ logic technology. This is a 10 nm technology featuring the third generation of Intel’s FinFETs, seventh generation of strained silicon, fifth generation of high
Autor:
J. Clifford, S. Ramey, C. Auth, Robert James, Anisur Rahman, A. St. Amour, Christopher J. Wiegand, Michael L. Hattendorf, J. Hicks, A. Ashutosh, Vyom Sharma
Publikováno v:
2013 IEEE International Reliability Physics Symposium (IRPS).
This paper highlights the intrinsic reliability capabilities of Intel's 22nm process technology, which introduced the tri-gate transistor architecture and features a 3rd generation high-κ/metal-gate process. Results are detailed from all traditional
Autor:
Christopher D. Thomas, Michael L. Hattendorf, Mark R. Brazier, K. Zawadzki, R. McFadden, P. Hentges, J. Seiple, W. Han, D. Ingerly, S. Jaloviar, Cory E. Weber, Huichu Liu, Robert James, C. Auth, C. Parker, Kaizad Mistry, M. Prince, V. Chikarmane, S. Ramey, J. Neirynck, A. Blattner, J. Roesler, M. Bost, P. Yashar, D. Hanken, J. Jopling, Ian R. Post, B. McIntyre, C. Kenyon, T. Troeger, S. Pradhan, Pulkit Jain, D. Towner, C. Allen, David Jones, J. Hicks, Timothy E. Glassman, J. Sandford, L. Pipes, R. Heussner, T. Reynolds, M. Buehler, Daniel B. Bergstrom, Tahir Ghani, Pete Smith, R. Grover, Subhash M. Joshi
Publikováno v:
2012 Symposium on VLSI Technology (VLSIT).
A 22nm generation logic technology is described incorporating fully-depleted tri-gate transistors for the first time. These transistors feature a 3rd-generation high-k + metal-gate technology and a 5th generation of channel strain techniques resultin
Autor:
Cory E. Weber, K. Kuhn, K. Zawadzki, Paul A. Packan, Roza Kotlyar, Tahir Ghani, Martin D. Giles, S. Cea, Pushkar Ranade, H. Deshpande, Oleg Golonzka, Anand Portland Murthy, Lucian Shifren, Michael L. Hattendorf
Publikováno v:
2008 IEEE International Electron Devices Meeting.
For the first time, the performance impact of (110) silicon substrates on high-k + metal gate strained 45 nm node NMOS and PMOS devices is presented. Record PMOS drive currents of 1.2 mA/um at 1.0 V and 100 nA/um Ioff are reported. It will be demonst
Autor:
V. Souw, Michael K. Harper, H. Mariappan, P. Vandervoorn, K. Tone, C. Auth, G. Glass, Timothy E. Glassman, Kaizad Mistry, A. Thompson, S. Jaloviar, Tahir Ghani, M. Lu, Nadia M. Rahhal-Orabi, Jason Klaus, J. Sandford, Christopher J. Wiegand, B. Norris, F. Tambwe, T. Troeger, D. Lavric, Pushkar Ranade, Michael L. Hattendorf, Annalisa Cappellani, Subhash M. Joshi, J.-S. Chun, J. Wiedemer, A. Dalis, K. Kuhn, P. Hentges, D. Towner, Charles H. Wallace, Alison Davis, Lucian Shifren
Publikováno v:
2008 Symposium on VLSI Technology.
Two key process features that are used to make 45 nm generation metal gate + high-k gate dielectric CMOS transistors are highlighted in this paper. The first feature is the integration of stress-enhancement techniques with the dual metal-gate + high-
Autor:
Tahir Ghani, M. Agostinelli, R. Chau, S. Ramey, Matthew V. Metz, Chetan Prasad, Christopher J. Wiegand, J. Sandford, J. Maiz, C. Thomas, Michael L. Hattendorf, M. Brazier, K. Kuhn, J. Wiedemer, G. Dewey, Jack Portland Kavalieros, S. Pae, A. Roskowski, Kaizad Mistry, J. Hicks, J. Thomas, Markus Kuhn
Publikováno v:
2008 IEEE International Reliability Physics Symposium.
In this paper, bias-temperature instability (BTI) characterization on 45nm high-K + metal-gate (HK+MG) transistors is presented and degradation mechanism is discussed. Transistors with an unoptimized HK film stack in the early development phase exhib
Autor:
Matthew V. Metz, K. Kuhn, S. Ramey, C. Auth, Tahir Ghani, Christopher J. Wiegand, R. Chau, B. McIntyre, G. Dewey, S. Pae, W. Rachmady, Markus Kuhn, J. Hicks, Jack Portland Kavalieros, A. Roskowski, Roza Kotlyar, J. Wiedemer, Chetan Prasad, J. Sandford, J. Maiz, J. Jopling, M. Agostinelli, M. Brazier, C. Thomas, Kaizad Mistry, Michael L. Hattendorf
Publikováno v:
2008 IEEE International Reliability Physics Symposium.
In this paper, we present extensive breakdown results on our 45nm HK+MG technology. Polarity dependent breakdown and SILC degradation mechanisms have been identified and are attributed gate and substrate injection effects. Processing conditions were
Autor:
P. Vandervoorn, D. Becher, Paul A. Packan, K. Kuhn, Michael L. Hattendorf, R. Basco, Ian R. Post, Ian A. Young
Publikováno v:
Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004..
RF CMOS performance from a 90nm derivative communications process technology is compared to SiGe BJT performance. NMOS performance at f/sub T//f/sub max/ = 209/248 GHz (70nm) and f/sub T//f/sub max/ = 166/277 GHz (80nm) with F/sub min/ at 0.3 dB (2GH