Zobrazeno 1 - 10
of 47
pro vyhledávání: '"Michael Eugene Givens"'
Autor:
Michael Eugene Givens, Mikko Ritala, Tom E. Blomberg, Suvi Haukka, Marko Tuominen, Simon D. Elliott, Suresh Kondati Natarajan, Varun Sharma
Funding Information: The authors thank Eurofins EAG Materials Science, LLC (California, USA) for the TEM analysis. S.K.N. thanks ICHEC and the Science Foundation Ireland funded computing center of Tyndall National Institute for computer time. S.K.N.
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::0cf60432dff29ef3691bdf600bffcf3a
https://aaltodoc.aalto.fi/handle/123456789/112919
https://aaltodoc.aalto.fi/handle/123456789/112919
Autor:
Mikko Ritala, Tom E. Blomberg, Suvi Haukka, Varun Sharma, Michael Eugene Givens, Marko Tuominen, Simon D. Elliott
Thermal atomic layer etching (ALEt) of amorphous Al2O3 was performed by alternate exposures of niobium pentafluoride (NbF5) and carbon tetrachloride (CCl4). The ALEt of Al2O3 is observed at temperatures from 380 to 460 degrees C. The etched thickness
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::ff1c691cd10c5d76b23653f4a6d79c67
http://hdl.handle.net/10138/343050
http://hdl.handle.net/10138/343050
Autor:
Ludovic Goux, R. Delhougne, Gouri Sankar Kar, Sven Van Elshocht, Christophe Detavernier, Wouter Devulder, Matty Caymax, Jan Willem Maes, Gabriel Khalil El Hajjam, Jean-Marc Girard, Karl Opsomer, Ali Haider, Johan Swerts, Shaoren Deng, Annelies Delabie, Michael Eugene Givens
Publikováno v:
MATERIALS ADVANCES
The ovonic threshold switch (OTS) selector based on the voltage snapback of amorphous chalcogenides has received tremendous attention as it provides several desirable characteristics such as bidirectional switching, a controllable threshold voltage,
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::e62b93c2d6d50a27c2fe78d325d76509
https://hdl.handle.net/1854/LU-8706073
https://hdl.handle.net/1854/LU-8706073
Autor:
Qi Xie, Ben Kaczer, Nadine Collaert, Jan Willem Maes, Dimitri Linten, Vamsi Putcha, Guido Groeseneken, Fu Tang, Jacopo Franco, Michael Eugene Givens, A. Vais
Gate-stack reliability has been a major roadblock in the realization of InGaAs-channel based logic technology. Excessive charge trapping in the gate-oxide causes time-dependent drift in transistor threshold voltage (Vth). The extent to which Vth drif
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::c6650095e5ab050550d4d2febbdf69e2
https://lirias.kuleuven.be/handle/123456789/683494
https://lirias.kuleuven.be/handle/123456789/683494
Autor:
Marc Heyns, Aaron Thean, Dan Mocuta, Laura Nyns, V. Putcha, Xiang Jiang, Jacopo Franco, Nadine Collaert, Arturo Sibaja Hernandez, Valentina Spampinato, Alexis Franquet, Dimitri Linten, Jerome Mitard, Sonja Sioncke, Fu Tang, Jan Willem Maes, Michael Eugene Givens, Qi Xie, Rita Rooyackers, A. Vais, Sergio Calderon Ardila
Publikováno v:
Advances in Science, Technology and Engineering Systems, Vol 3, Iss 5, Pp 36-44 (2018)
In this work, we discuss how the insertion of a LaSiOx layer in between an in-house IL passivation layer and the high-k has moved the III-V gate stack into the target window for future technology nodes. The insertion of this LaSiOx layer in the gate
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::2f90282291f65b09e4873a69c32b11c9
https://astesj.com/v03/i05/p06/
https://astesj.com/v03/i05/p06/
Autor:
Dennis Lin, Sonja Sioncke, Xiaoqiang Jiang, V. Putcha, Nadine Collaert, Kristin De Meyer, Aaron Thean, Fu Tang, Laura Nyns, Michael Eugene Givens, A. Vais, Jacopo Franco, Qi Xie, Anda Mocuta, Jan Willem Maes, Koen Martens
Publikováno v:
IEEE Electron Device Letters. 38:318-321
This letter proposes a metric to assess the quality of high-k dielectrics on III–V substrates and a benchmarking methodology for the gate stack qualification in the region of MOS device operation above threshold voltage, ${V}_{t}$ . The metric is b
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::a34f3f0f4d5898224719859f7489d1ac
https://doi.org/10.1109/led.2017.2657794
https://doi.org/10.1109/led.2017.2657794
Autor:
Jerome Mitard, Jan Willem Maes, Dan Mocuta, Rita Rooyackers, Fu Tang, A. Vais, Nadine Collaert, Qi Xie, J. Franco, Valentina Spampinato, Laura Nyns, S. Calderon Ardila, Alexis Franquet, D. Linten, M.M. Heyns, Michael Eugene Givens, Xiaoqiang Jiang, Aaron Thean, A. Sibaja-Hernandez, V. Putcha, Sonja Sioncke
Publikováno v:
2017 Symposium on VLSI Technology.
In this paper, we demonstrate for the first time an implant free In 0.53 Ga 0.47 As n-MOSFET that meets the reliability target for advanced technology nodes with a max operating V ov of 0.6 V. In addition, an excellent electron mobility (μ eff, peak
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::3b9f19a245dd4fb1e9fff26c9f9c84ec
https://doi.org/10.23919/vlsit.2017.7998192
https://doi.org/10.23919/vlsit.2017.7998192
Autor:
J. Franco, Lars-Ake Ragnarsson, Michael Eugene Givens, Sonja Sioncke, A. Subirats, D. Linten, V. Putcha, B. Kaczer, Fu Tang, Liesbeth Witters, Anne Vandooren, Nadine Collaert, A. Vais, Naoto Horiguchi, Xiaoqiang Jiang, Qi Xie, Hiroaki Arimura, Adrian Chasin
Publikováno v:
2017 IEEE International Reliability Physics Symposium (IRPS).
3D Sequential integration has been envisioned to stack transistors in the same front-end process. A crucial challenge is the management of the thermal budget. This work focuses on Si nMOS gate stack challenges, specifically: for a top tier device, by
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::97afea5a05349ab16ed23a2d481fac4b
https://doi.org/10.1109/irps.2017.7936259
https://doi.org/10.1109/irps.2017.7936259
Autor:
Sonja Sioncke, Qi Xie, V. Putcha, Xiaoqiang Jiang, Ben Kaczer, Dimitri Linten, Michael Eugene Givens, Jacopo Franco, Pauline Calka, Fu Tang, Nadine Collaert, Guido Groeseneken, A. Vais
Publikováno v:
2017 IEEE International Reliability Physics Symposium (IRPS).
In this work, we show that the reliability of InGaAs channel MOS devices not only depends on density of shallow defect states (i.e., electron traps responsible for PBTI in Si devices), but it is also governed by the density of deep defect states. Thi
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::1304c20d36a2e181f14073c4fd5fad8f
https://doi.org/10.1109/irps.2017.7936422
https://doi.org/10.1109/irps.2017.7936422
Autor:
Kurt Wostyn, Xiaoqiang Jiang, Lars-Ake Ragnarsson, Jan Willem Maes, E. Chiu, Daire J. Cott, A. Sibaja-Hernandez, Michael Eugene Givens, X. Lu, J. Geypen, Jacopo Franco, Roger Loo, Nadine Collaert, W. Vanherle, Hugo Bender, Dan Mocuta, Jerome Mitard, Fu Tang, Guillaume Boccardi, Hiroaki Arimura, Sonja Sioncke, Qi Xie
Publikováno v:
Web of Science
We demonstrate a Si-passivated Ge nMOS gate stack with Dit of ∼5×1010 cm−2eV−1 around midgap and unnoticeable C-V hysteresis at an operating condition (oxide trap density of ∼1×108 cm−2 at V ov /CET=3.5 MV/cm). Insertion of a 3D-compatibl
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::91782190d738b9e6dfd3b85b6fe06d00
https://doi.org/10.1109/iedm.2016.7838534
https://doi.org/10.1109/iedm.2016.7838534