Zobrazeno 1 - 10
of 47
pro vyhledávání: '"Michael D. Hutton"'
Autor:
Jason H. Anderson, João M. P. Cardoso, Guy Gogniat, JunKyu Lee, Hayden K.-H. So, Tero Rissa, Patrick Lysaght, Hideharu Amano, Philip H. W. Leong, Oliver Diessel, Koen Bertels, Yu Wang, Wayne Luk, Michael D. Hutton, Marco Platzner, Cristina Silvano, Viktor K. Prasanna
A summary of contributions made by significant papers from the first 25 years of the Field-Programmable Logic and Applications conference (FPL) is presented. The 27 papers chosen represent those which have most strongly influenced theory and practice
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::7929d17fb82eddcfacf895d7191ca5b5
http://hdl.handle.net/11311/1076746
http://hdl.handle.net/11311/1076746
Publikováno v:
Embedded Systems Design and Verification
Since their introduction in the early 1980s, Field-Programmable Gate Arrays (FPGAs) have evolved from implementing small glue-logic designs to implementing large complete systems. Programmable logic devices range from lower-capacity nonvolatile devic
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::f3d63a6a02d90791b126f735430e3b07
https://doi.org/10.1201/b19714-18
https://doi.org/10.1201/b19714-18
Autor:
Michael D. Hutton
Publikováno v:
Proceedings of the 2016 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays.
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::dd5232939b4eff8f123d5e4ec0f4fe27
https://doi.org/10.1145/3250861
https://doi.org/10.1145/3250861
Publikováno v:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 16:124-133
Process variation and prerouting interconnect delay uncertainty affect timing and power for modern VLSI designs in nanometer technologies. This paper presents the first in-depth study on stochastic physical synthesis algorithms leveraging statistical
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::30a0097422596984f806039c97c60c53
https://doi.org/10.1109/tvlsi.2007.912027
https://doi.org/10.1109/tvlsi.2007.912027
Autor:
Michael D. Hutton, Hae-Chang Lee, Jeffrey Tyhach, Dong-myung Choi, Arifur Rahman, Edwin Yew Fatt Kok, Jack Chui, Martin Langhammer, Boon-Jin Ang, David Lewis, Ket Chiew Sia, Wei-Yee Koay, Tim Tri Hoang, Dan Oh, Brad Vest, Atsatt Sean R, Sergey Shumarayev, Allen Chan
Publikováno v:
CICC
This paper presents the architecture of Arria 10, a high-density FPGA family built on the TSMC 20SOC process. The design of the device includes an embedded dual-core 1.5 GHz ARM A9 subsystem with peripherals, more than 1M logic elements (LEs) and 1.7
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::f669d6ca77fda7c7765504731bc990e9
https://doi.org/10.1109/cicc.2015.7338368
https://doi.org/10.1109/cicc.2015.7338368
Autor:
Michael D. Hutton
Publikováno v:
Hot Chips Symposium
This article consists of a collection of slides from the author's conference presentation. Summary points include: 3D integration isn't just integration, it is - De-risking, process matching, derivative proliferation and tick/tock; Device floorplanni
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::5167cec21a4dd76d882ee6c8c985fea5
https://doi.org/10.1109/hotchips.2015.7477458
https://doi.org/10.1109/hotchips.2015.7477458
Autor:
Hongyu Chen, Michael D. Hutton, Peter Suaris, T. Collins, Shuo Zhou, Nan-Chi Chou, Bo Yao, Chung-Kuan Cheng, S. Srinivasan, Yi Zhu
Publikováno v:
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 26:959-969
We improve the efficiency of static timing analysis when false paths are considered. The efficiency of timing analysis is critical for the performance driven optimization program because timing analysis is invoked heavily in the inner loop. However,
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::872f8d4f2c3b50708dbe9845abbe036c
https://doi.org/10.1109/tcad.2006.885737
https://doi.org/10.1109/tcad.2006.885737
Publikováno v:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 11:60-63
This paper describes the application of weighted partitioning techniques to timing-driven placement on a hierarchical programmable logic device. We discuss the nature of placement on these architectures, the details of applying weighted techniques sp
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::2cdcc080cd73bb00588bf634087f515b
https://doi.org/10.1109/tvlsi.2002.808424
https://doi.org/10.1109/tvlsi.2002.808424
Autor:
Koen Bertels, Patrick Lysaght, Michael D. Hutton, JunKyu Lee, Yu Wang, João M. P. Cardoso, Oliver Diessel, Wayne Luk, Tero Rissa, Jason H. Anderson, Hideharu Amano, Marco Platzner, Guy Gogniat, Hayden K.-H. So, Philip H. W. Leong, Cristina Silvano, Viktor K. Prasanna
Publikováno v:
FPL
The list of significant papers from the first 25 years of the Field-Programmable Logic and Applications conference (FPL) is presented in this paper. These 27 papers represent those which have most strongly influenced theory and practice in the field.
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::b80e466b2d25fd2a7689594a64e5d65f
http://hdl.handle.net/11311/988875
http://hdl.handle.net/11311/988875
Publikováno v:
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 21:928-940
The design of programmable logic architectures and supporting computer-aided design tools fundamentally requires both a good understanding of the combinatorial nature of netlist graphs and sufficient quantities of realistic examples to evaluate or be
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::35ec08f9746b1022766386d62980e24a
https://doi.org/10.1109/tcad.2002.800456
https://doi.org/10.1109/tcad.2002.800456