Zobrazeno 1 - 10
of 72
pro vyhledávání: '"Michael A. Kochte"'
Autor:
Hans-Joachim Wunderlich, Eric Schneider, Chang Liu, Matthias Kampmann, Michael A. Kochte, Sybille Hellebrand
Publikováno v:
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 38:1956-1968
Marginal hardware introduces severe reliability threats throughout the life cycle of a system. Although marginalities may not affect the functionality of a circuit immediately after manufacturing, they can degrade into hard failures and must be scree
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::5bd52a7db130fe90659267beecbe3dfd
https://doi.org/10.1109/tcad.2018.2864255
https://doi.org/10.1109/tcad.2018.2864255
Publikováno v:
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 38:309-321
This paper presents a novel test architecture that combines the advantages of high-quality deterministic scan-based test and low-cost built-in self-test. The main idea is to record (store) all required compressed test data in a novel scan chain struc
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::40c7862589956812fbcb90b7c7ff2033
https://doi.org/10.1109/tcad.2018.2808241
https://doi.org/10.1109/tcad.2018.2808241
Autor:
Hans-Joachim Wunderlich, Eric Schneider, Jorg Henkel, Lars Bauer, Hongyan Zhang, Michael A. Kochte
Publikováno v:
Dependable Embedded Systems ISBN: 9783030520168
Runtime/reconfigurable architectures based on Field-Programmable Gate Arrays (FPGAs) are a promising augment to conventional processor architectures such as Central Processing Units (CPUs) and Graphic Processing Units (GPUs). Since the reconfigurable
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::454408b934d13fcbb7eb2ca49f1225a8
https://doi.org/10.1007/978-3-030-52017-5_12
https://doi.org/10.1007/978-3-030-52017-5_12
Publikováno v:
DATE
On-chip instrumentation is mandatory for efficient bring-up, test and diagnosis, post-silicon validation, as well as in-field calibration, maintenance, and fault tolerance. Reconfigurable scan networks (RSNs) provide a scalable and efficient scan-bas
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::8aa64f64fa00aaaa763f8b921a42d0e9
https://doi.org/10.23919/date48585.2020.9116525
https://doi.org/10.23919/date48585.2020.9116525
Publikováno v:
IEEE Design & Test. 35:7-18
Editor’s note: Self-testing hardware has a long tradition as a complement to manufacturing testing based on test stimuli and response analysis. Today, it is a mature field and many complex SoCs have self-testing structures built-in (BIST). For self
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::3da94f296fea0d39a2d38fc2750a17c9
https://doi.org/10.1109/mdat.2017.2762903
https://doi.org/10.1109/mdat.2017.2762903
Built-In Test and Diagnosis for TSVs With Different Placement Topologies and Crosstalk Impact Ranges
Publikováno v:
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 36:1004-1017
Through silicon vias (TSVs) play an important role in 3-D chip integration. Effective and efficient testing for correct operation of TSVs is essential for 3-D integrated circuit design. This paper addresses the post-bond test and diagnosis of crossta
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::89a3f2aaf25c0f515e63b3a865133a50
https://doi.org/10.1109/tcad.2016.2613928
https://doi.org/10.1109/tcad.2016.2613928
Autor:
Hans-Joachim Wunderlich, Lars Bauer, Jorg Henkel, Eric Schneider, Hongyan Zhang, Michael A. Kochte
Publikováno v:
IEEE Transactions on Computers. 66:957-970
Runtime reconfigurable architectures based on Field-Programmable Gate Arrays (FPGAs) allow area- and power-efficient acceleration of complex applications. However, being manufactured in latest semiconductor process technologies, FPGAs are increasingl
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::7d2dde2b6933411ffc9bb81b352feb30
https://doi.org/10.1109/tc.2016.2616405
https://doi.org/10.1109/tc.2016.2616405
Publikováno v:
ITC
With today's tight timing margins, increasing manufacturing variations, and new defect behaviors in FinFETs, effective yield learning requires detailed information on the population of small delay defects in fabricated chips. Small delay fault diagno
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::bfafc8833d360749de3ae89ffb0029bc
https://doi.org/10.1109/itc44170.2019.9000143
https://doi.org/10.1109/itc44170.2019.9000143
Autor:
Hans-Joachim Wunderlich, Hongyan Zhang, Jorg Henkel, Michael A. Kochte, Lars Bauer, Eric Schneider
Publikováno v:
Many-Core Computing: Hardware and Software ISBN: 9781785615825
The chapter discusses the background for the most demanding dependability challenges for reconfigurable processors in many-core systems and presents a dependable runtime reconfigurable processor for high reliability. It uses an adaptive modular redun
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::1d4b79561e10c79e1a0a8b4eb60d0c11
https://doi.org/10.1049/pbpc022e_ch16
https://doi.org/10.1049/pbpc022e_ch16
Autor:
Seiji Kajihara, Michael A. Kochte, Xiaoqing Wen, Stefan Holst, K. Asada, Jun Qian, Hans-Joachim Wunderlich, Eric Schneider, Kohei Miyase
Publikováno v:
ATS
IR-drop induced by launch switching activity (LSA) in capture mode during at-speed scan testing increases delay along not only logic paths (LPs) but also clock paths (Cps). Excessive extra delay along LPs compromises test yields due to false capture
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::ab5da88a2b4aa6fe340eab91b25f7e0a
https://kyutech.repo.nii.ac.jp/records/6375
https://kyutech.repo.nii.ac.jp/records/6375