Zobrazeno 1 - 10
of 14
pro vyhledávání: '"Merritt Funk"'
Autor:
Blake R Parkinson, Asao Yamashita, Merritt Funk, Thomas F. Edgar, Radha Sundararajan, Hyung Lee, Daniel J. Prager
Publikováno v:
IEEE Transactions on Semiconductor Manufacturing. 23:185-193
Multivariate plasma etch modeling and control methodology are presented based on 65 and 45 nm gate production data utilizing wafer-to-wafer tool-level scatterometry. The selection of etch recipe variables for optimal control of wafer-to-wafer profile
Autor:
Demetre J. Economou, Merritt Funk, Radha Sundararajan, Lee Chen, Zhiying Chen, Vincent M. Donnelly
Publikováno v:
Journal of Vacuum Science & Technology A: Vacuum, Surfaces, and Films. 27:1159-1165
Measurements of electron temperatures (Te) and electron energy distribution functions (EEDFs) in a dual frequency capacitively coupled etcher were performed by using trace rare gas optical emission spectroscopy (TRG-OES). The parallel plate etcher wa
Publikováno v:
2015 IEEE International Symposium on Antennas and Propagation & USNC/URSI National Radio Science Meeting.
The paper presents the analysis of propagation and scattering in a microwave plasma chamber. The chamber consists of a looped circular waveguide with the TE11 mode excited by the TE10 mode from a linear rectangular waveguide. The microwave power extr
Autor:
Eric Meyette, Merritt Funk, Radha Sundararajan, Blake R Parkinson, Dan Prager, Kenneth A. Bandy, Asao Yamashita
Publikováno v:
Metrology, Inspection, and Process Control for Microlithography XXIII.
As die feature sizes continue to decrease, advanced process control has become essential for controlling profile and CD uniformity across the wafer. Gate CD variation must be suppressed by process optimization of lithography, photoresist trim, and ga
Autor:
Merritt Funk, Radha Sundararajan, Asao Yamashita, Kenneth A. Bandy, Dan Prager, Alok Ranjan, Anita Viswanathan, Eric Meyette, Hyung Mok Lee
Publikováno v:
SPIE Proceedings.
Gate patterning is critical to the final yield and performance of logic devices. Because of this, gate linewidth control is viewed by many as the most critical application for integrated metrology on etch systems. For several years, integrated metrol
Publikováno v:
2006 IEEE International Symposium on Semiconductor Manufacturing.
The current technology node and the complexity of device design and processing demand metrology systems that can provide profile and underlying layer information in one measurement; and perform this task with high accuracy and precision. Additionally
Publikováno v:
SPIE Proceedings.
For several years, integrated scatterometry has held the promise of wafer-level process control. While integrated scatterometry on lithography systems is being used in manufacturing, production implementation on etch systems is just beginning to occu
Autor:
Merritt Funk, Qingyun Yang, Joyce C. Liu, Matthew Sendelbach, Jeffrey S. Brown, Daniel J. Prager, Peter E. Cottrell, David V. Horak, Eric P. Solecky, Randy W. Mann, Sadanand V. Deshpande, Wesley C. Natzle, F. Higuchi, Chienfan Yu, Hussein I. Hanafi, Akihisa Sekiguchi, Subramanian S. Iyer, W. Yan, Bruce B. Doris, Masayuki Tomoyasu, James P. Norum, Len Y. Tsou, Asao Yamashita, Hiroyuki Takahashi
Publikováno v:
2004 IEEE/SEMI Advanced Semiconductor Manufacturing Conference and Workshop (IEEE Cat. No.04CH37530).
A method for formation and control of silicon gates or fins uses trim of a hard mask by a new gaseous oxide etch. The method decouples final feature size from lithography and from the RIE resist trim/oxide mask open processes. Logic blocks with two s
Autor:
Bill Banke, Merritt Funk, Wesley C. Natzle, Dan Prager, Charles N. Archie, Jason Ferns, Matthew Sendelbach, Dan Engelhard, Fumihiko Higuchi, Asao Yamashita, Masayuki Tomoyasu
Publikováno v:
Metrology, Inspection, and Process Control for Microlithography XVIII.
As feature geometries decrease, the budgeted error for process variations decreases as well. Keeping these variations within budget is especially important in the area of gate linewidth control. Because of this, wafer-to-wafer control of gate linewid
Publikováno v:
SPIE Proceedings.
New 300mm facilities are decreasing start-up risks by developing new processes on 200mm equipment and transferring the process and manufacturing methods to the 300mm line. 200mm factories have stable processes, equipment and manufacturing methods. Le