Zobrazeno 1 - 9
of 9
pro vyhledávání: '"Meng-Jye Hu"'
Autor:
Meng-Jye Hu, 胡孟杰
92
In this paper, we discuss several applications of remote sensing image analysis. Unlike the traditional color image, remote sensing image is acquired by the sensor comprises a number of bands, each of which represents the intensity of an imag
In this paper, we discuss several applications of remote sensing image analysis. Unlike the traditional color image, remote sensing image is acquired by the sensor comprises a number of bands, each of which represents the intensity of an imag
Externí odkaz:
http://ndltd.ncl.edu.tw/handle/74018830484238350193
Autor:
Chun-Chia Chen, Tsu-Ming Liu, Min-Hao Chiu, Tung-Hsing Wu, Chi-cheng Ju, Wei-Cing Li, Yen-Chieh Lai, Yi-Hsin Huang, Peng-Hao Wang, Yen-Chao Huang, Chih-Ming Wang, Ping Chao, Hsiu-Yi Lin, Ming-Long Wu, Meng-Jye Hu, Yu-Kun Lin, Ting-An Lin, Chia-Yun Cheng, Che-Hong Chen, Sheng-Jen Wang, Shun-Hsiang Chuang, Han-Liang Chou, Chen Lien-Fei, Hue-Min Lin, Yung-Chang Chang, Chih-Da Chien, Kun-bin Lee
Publikováno v:
IEEE Journal of Solid-State Circuits. 51:56-67
A 4 K $\,\times\,$ 2 K H.265/HEVC video codec chip supporting 14 video standard formats is implemented on a 1.49 $\,\times\,$ 1.45 mm $^{2}$ die in a 28 nm CMOS process. Several HEVC fast algorithms reduce the coding modes by analyzing the content fe
Autor:
Hsiao-En Chen, Ping Chao, Min-Hao Chiu, Hue-Min Lin, Chen Yi-Chang, Hsiu-Yi Lin, Chih-Wen Yang, Yung-Chang Chang, Shun-Hsiang Chuang, Meng-Jye Hu, Chi-cheng Ju, Chia-Yun Cheng, Fu-Chun Yeh, Che-Hong Chen, Peng Hsuan-Wen, Sheng-Jen Wang, Yenchieh Huang, Chun-Chia Chen, Chih-Ming Wang, Ming-Long Wu, Kao Chia-Hung, Tsu-Ming Liu, Chia-Lin Ho
Publikováno v:
ESSCIRC
A lower power and area efficient VP9 and multi-standard video decoder chip is first-reported for Android 4K TV. It supports prevalent MPEG-x, VP-x, RMx, WMV-x and H.26x series video standards in a single chip. Three high-throughput techniques, look-a
Autor:
Chia-Lin Ho, Ping Chao, Hsiu-Yi Lin, Che-Hong Chen, Min-Hao Chiu, Hue-Min Lin, Chun-Chia Chen, Ming-Long Wu, Tsu-Ming Liu, Chia-Yun Cheng, Fu-Chun Yeh, Shun-Hsiang Chuang, Chi-cheng Ju, Chih-Ming Wang, Yung-Chang Chang, Sheng-Jen Wang, Meng-Jye Hu
Publikováno v:
ICME
A 4K and Main-10 HEVC video decoder LSI is fabricated in a 28nm CMOS process. It adopts a block-concealed processor (BcP) to improve the visual quality and a bandwidth-suppressed processor (BsP) is newly designed to reduce 30% and 45% of external dat
Autor:
Min-Hao Chiu, Yu-Kun Lin, Peng-Hao Wang, Tsu-Ming Liu, Yen-Chao Huang, Ping Chao, Kun-bin Lee, Han-Liang Chou, Hue-Min Lin, Chen Lien-Fei, Ryan Chen, Yung-Chang Chang, Ming-Long Wu, Kevin Jou, Wei-Cing Li, Yen-Chieh Lai, Yi-Hsin Huang, Che-Hong Chen, Tung-Hsing Wu, H Y Hsu, Sheng-Jen Wang, Chih-Da Chien, Ting-An Lin, Shun-Hsiang Chuang, Chun-Chia Chen, Chi-cheng Ju, Hsiu-Yi Lin, Chin-Ming Wang, Meng-Jye Hu, Chia-Yun Cheng, Fu-Chun Yeh
Publikováno v:
ISSCC
A 4K×2K H.265/HEVC video codec chip is fabricated in a 28nm CMOS process with a core area of 2.16mm2. This LSI chip integrates a dual-standard (H.265 and H.264) video codec and a series of prevalent (VC-1, WMV-7/8/9, VP-6/8, AVS, RM-8/9/10, MPEG-2/4
Autor:
Min-Hao Chiu, Hsiu-Yi Lin, Che-Hong Chen, Chung-Hung Tsai, Chi-cheng Ju, Chia-Yun Cheng, Fu-Chun Yeh, Ping Chao, Tsu-Ming Liu, Chun-Chia Chen, Shun-Hsiang Chuang, Hue-Min Lin, Meng-Jye Hu, Chih-Ming Wang, Yung-Chang Chang, Ming-Long Wu, Sheng-Jen Wang
Publikováno v:
ESSCIRC
a first-reported 4Kx2K@60fps and Main-10 HEVC video decoder integrating 14 video formats is fabricated in a 28nm CMOS process. It adopts an Adaptive Coding Unit Balance (ACUB) and Data-Sharing Wave-front Dual-core (DSWD) architectures to lower the re
Autor:
Chun-Chia Chen, Ping Chao, Huaide Wang, Min-Hao Chiu, Chia-Yun Cheng, Chang-Lin Hsieh, Hue-Min Lin, Ryan Yeh, Chih-Ming Wang, Hsiu-Yi Lin, Chung-Hung Tsai, Ted Chuang, Yung-Chang Chang, Chi-cheng Ju, Tsu-Ming Liu, Sheng-Jen Wang, Brian Liu, Meng-Jye Hu
Publikováno v:
VLSIC
A first-reported 4K×2K@60fps digital TV SoC processor supporting 9 video formats and integrating HDMI/MHL receiver is fabricated in a 40nm CMOS process. It adopts error compensation processor (ECP) to improve the visual quality, and designs a memory
Autor:
Ping Chao, Hue-Min Lin, Sheng-Jen Wang, Min-Hao Chiu, Chia-Yun Cheng, Tsu-Ming Liu, Chun-Chia Chen, Chi-cheng Ju, Chih-Ming Wang, Hao-Wei Li, Meng-Jye Hu, Yung-Chang Chang, Chung-Hung Tsai
Publikováno v:
ISCAS
A first-reported, sub-mW/fps/view multi-view video decoder chip fully compliant to 3D Blu-ray specifications is reported. It explores the resource sharing so as to integrate not only single-view MPEG-2/VC-1/AVC but multi-view MVC standards into a sin
Autor:
Meng-Jye, Hu
Thesis (M.A.)--National Taiwan University Graduate Institute of Communication Engineering
Includes bibliographical references
Includes bibliographical references