Zobrazeno 1 - 10
of 25
pro vyhledávání: '"Meng-Chiou Wu"'
Publikováno v:
Simulated Annealing
As semiconductor process technology relentlessly advances into deeper submicron feature sizes following the Moore’s Law, the cost of mask tooling is growing inexorably, up to 1, 1.5, and 3 million dollars for 90nm, 65nm, and 32nm process technology
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::4d0650129b91ed08c492cc6e570a564f
http://www.intechopen.com/articles/show/title/reticle_floorplanning_and_simulated_wafer_dicing_for_multiple-project_wafers_by_simulated_annealing
http://www.intechopen.com/articles/show/title/reticle_floorplanning_and_simulated_wafer_dicing_for_multiple-project_wafers_by_simulated_annealing
Publikováno v:
International Journal of High Performance Computing and Networking. 14:237
The emergence of the internet has resulted in the relative expansion of complicated network architecture. Accordingly, the traditional network architecture can no longer meet the demand of a new and rapidly changing network service. Given the emergen
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::06e1c9e0588889b96aaedd5ffbf233d0
https://doi.org/10.1504/ijhpcn.2019.10022739
https://doi.org/10.1504/ijhpcn.2019.10022739
Autor:
Rung-Bin Lin, Meng-Chiou Wu
Publikováno v:
Journal of Circuits, Systems and Computers. 17:15-31
Multiple project wafers (MPWs) containing different chip designs from many customers serves as an important vehicle for gaining access to advanced semiconductor process technology for prototyping innovative designs or low-volume production. In this p
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::cb5877b5db3412d3a3ad94838f636f41
https://doi.org/10.1142/s0218126608004186
https://doi.org/10.1142/s0218126608004186
Publikováno v:
ACM Transactions on Design Automation of Electronic Systems. 13:1-21
Chip placement in a reticle is crucial to the cost of a multiproject wafer run. In this article we develop several chip placement methods based on the volume-driven compatibility optimization (VOCO) concept, which maximizes dicing compatibility among
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::67695c68c1be04f53922ccc8a67e9824
https://doi.org/10.1145/1297666.1297688
https://doi.org/10.1145/1297666.1297688
Publikováno v:
IEEE Transactions on Automation Science and Engineering. 4:589-595
Multiproject wafer (MPW) production cost is sensitive to how the chips are arranged in a reticle. In this paper, we propose a methodology for exploring the reticle floorplan design space to minimize MPW production cost. Experimental results show that
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::802766e1d729984bdfcaec894fa092e9
https://doi.org/10.1109/tase.2007.904239
https://doi.org/10.1109/tase.2007.904239
Publikováno v:
SPIE Proceedings.
The mask set for a shuttle run (multi-project wafer) may contain designs using different number of metal layers. Wafers fabricated with k metal layers can only yield dice for the designs using only k metal layers. This results in considerable waste o
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::b735245392c1be1daa3deb08e85fc449
https://doi.org/10.1117/12.743377
https://doi.org/10.1117/12.743377
Publikováno v:
DDECS
A reticle exposure plan for a multi-project wafer (MPW) defines the sites where reticle images are printed on the wafer. In this paper, we propose an approach to finding a reticle exposure plan that minimizes the wafer fabrication cost rather than th
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::bec2505f16d81d1fc832ad523dac4666
https://doi.org/10.1109/ddecs.2007.4295308
https://doi.org/10.1109/ddecs.2007.4295308
Publikováno v:
2006 International Symposium on VLSI Design, Automation and Test.
Floorplanning chips in more than one reticle for multi-projcet wafers has not been investigated. In this paper, we propose two approaches to this problem. We first formulate this problem with pre-selected reticle sizes as a mixed-integer linear progr
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::903fbec62ce84a730fb876e8f93e2175
https://doi.org/10.1109/vdat.2006.258145
https://doi.org/10.1109/vdat.2006.258145
Publikováno v:
Asia and South Pacific Conference on Design Automation, 2006..
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::1563708746718c83d95fbc09a01abbd2
https://doi.org/10.1109/aspdac.2006.1594781
https://doi.org/10.1109/aspdac.2006.1594781
Publikováno v:
ASP-DAC
Chip floorplan in a reticle for Multi-Project Wafer (MPW) plays a key role in deciding chip fabrication cost. In this paper, we propose a methodology to explore reticle flooplan design space to minimize MPW production cost, facilitated by a new cost
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::68baa890c89b988a3cdebb0250b4f6cc
https://doi.org/10.1145/1118299.1118479
https://doi.org/10.1145/1118299.1118479