Versatile FPGA-Based Functional Validation Framework for Networks-on-Chip Interconnections Designs

Autor: Perez Ramas, J. B., Atienza, D., Peón, M., Magán, I., Mendías, J. M., Hermida, R.

Publikováno v: Jülich : John von Neumann Institute for Computing, NIC series 33, 769-776 (2006).
NIC Series Volume 33 : Parallel Computing: Current & Future Issues of High-End Computing, Proceedings of the International Conference ParCo 2005, G.R. Joubert, W.E. Nagel, F.J. Peters, O. Plata, P. Tirado, E. Zapata (Editors), chapter 100, p. 769-776, Jülich : John von Neumann Institute for Computing, 2006. ISBN: 3-00-017352-8

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=od______3364::a16339914f1072aaa638b433579926ff
https://hdl.handle.net/2128/6340

Tento výsledek nelze pro nepřihlášené uživatele zobrazit.
K zobrazení výsledku je třeba se přihlásit.

Bit-level scheduling of heterogeneous behavioural specifications.

Autor: Molina, M. C., Mendías, J. M., Hermida, R.

Publikováno v: Proceedings of the 2002 IEEE ACM International Conference Computer-aided Design; 11/10/2002, p602-608, 7p

Execution condition analysis in high level synthesis.

Autor: Peñalba, O., Mendías, J. M., Molina, M. C.

Publikováno v: International Symposium on Systems Synthesis; Jan2000, p73-78, 6p

Behavioural Bitwise Scheduling Based on Computational Effort Balancing.

Autor: Molina, M. C., Ruiz-Sautua, R., Mendías, J. M., Hermida, R.

Publikováno v: Proceedings of the Conference: Design, Automation & Test in Europe; 2/16/2004, p10684, 1p