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pro vyhledávání: '"Memory rank"'
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Autor:
Nagi Mekhiel
Publikováno v:
IEEE Access, Vol 4, Pp 1073-1085 (2016)
The increase in processor speed achieved by continuous improvements in technology is causing major obstacles to the parallel processors implemented inside the chip. The time spent in servicing all the cache misses from all processors from a slow shar
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::9707809215befd5c7926517fcf57f4d1
https://doi.org/10.32920/21463020
https://doi.org/10.32920/21463020
Autor:
Wooyoung Jang
Publikováno v:
IEEE Transactions on Circuits and Systems for Video Technology. 28:3527-3538
The state-of-the-art mobile image and graphic applications demand not only a lot of computing power, but also high-quality memory services. Moreover, depending on the screen orientations of mobile systems, image and graphic data can be accessed in a
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::07089fe5cebe4447aa46367d15f164f1
https://doi.org/10.1109/tcsvt.2017.2715062
https://doi.org/10.1109/tcsvt.2017.2715062
Publikováno v:
IEEE Transactions on Computers. 67:32-44
For future exascale computing systems, ultra-high-density memories would be required that consume low power to process massive data. Of the various memory devices, 3D-stacked DRAMs using TSVs are a perfect solution for this purposes. In addition to p
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::fb335ada2e8b066f8a7e0ba91f5b6616
https://doi.org/10.1109/tc.2017.2723392
https://doi.org/10.1109/tc.2017.2723392
Autor:
Stefan Dietrich, Marcos Alvarez Gonzalez, Milena Ivanov, Mani Balakrishnan, Michael Richter, Filippo Vitale, Jorg Weller, Wolfgang Spirkl, Ralf Oliver Seitter, Sven Piatkowski, Jens Polney, Peter Pfefferl, Cristian Chetreanu, Manfred Plan, Marc Walter, Daniel Lauber, Eugen Huber, Stephan Rau, Swetha Padaraju, Thomas Hein, Maksim Kuzmenka, Martin Broschwitz, Jan Pottgiesser, Martin Brox, Ronny Schneider, Fabien Funfrock, Christian N. Mohr, Juan Ocon Garrido
Publikováno v:
IEEE Journal of Solid-State Circuits. 53:134-143
The graphic DRAM interface standard GDDR5X is developed as an evolutionary extension to the widely available GDDR5. The implementation presented here achieves a data rate of 12 Gb/s/pin on a single-ended signaling interface with 32 IOs for a total me
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::6f1ac33fd7c18539aa948a4a0775950d
https://doi.org/10.1109/jssc.2017.2737945
https://doi.org/10.1109/jssc.2017.2737945
Publikováno v:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 25:3251-3254
Initializing memory with zero data is essential for safe memory management. However, initializing a large memory area slows down the system significantly. The most likely cause for initialization to slow down the system is the limited DRAM initializa
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::0f3d322f5852ff685c82350849e91acf
https://doi.org/10.1109/tvlsi.2017.2737646
https://doi.org/10.1109/tvlsi.2017.2737646
Publikováno v:
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 36:1458-1470
Phase change memory (PCM), given its nonvolatility, potential high density, and low standby power, is a promising candidate to be used as main memory in next generation computer systems. However, to hide its shortcomings of limited endurance and slow
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::443624ec166f44d5842d77a4ecd6d9f4
https://doi.org/10.1109/tcad.2016.2615845
https://doi.org/10.1109/tcad.2016.2615845
Publikováno v:
IEEE Transactions on Industrial Informatics. 13:1951-1960
The increasing demand on the main memory capacity is one of the main big data challenges. Dynamic random access memory (DRAM) does not represent the best choice for a main memory, due to high power consumption and low density. However, the nonvolatil
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::92330e8eab2d6e80e6de94f99508f62f
https://doi.org/10.1109/tii.2016.2645941
https://doi.org/10.1109/tii.2016.2645941
Autor:
Bing-Yang Lin, Ching-Nen Peng, Cheng-Wen Wu, Hung-Chih Lin, Min-Jer Wang, Hsuan-Hung Liu, Wan-Ting Chiang, Lee Mincent
Publikováno v:
IEEE Transactions on Computers. 66:1293-1301
Redundancy repair is a commonly used technique for memory yield improvement. In order to ensure high repair rate and final product yield, it is necessary to develop a repair scheme for the coming three-dimensional (3D) architecture of stacked DRAM. A
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::a3d67ed19f52cdac08bb0e6aadf441c4
https://doi.org/10.1109/tc.2017.2667645
https://doi.org/10.1109/tc.2017.2667645
Autor:
Jaemin Jang, Jungwhan Choi, Jinwoong Suh, Lee-Sup Kim, Young-Suk Moon, Yongkee Kwon, Wongyu Shin
Publikováno v:
IEEE Transactions on Computers. 66:1274-1280
DRAM systems are hierarchically organized: Channel-Rank-Bank. A channel is connected to multiple ranks, and each rank has multiple banks. This hierarchical structure facilitates creating parallelisms in DRAM. The current DRAM architecture supports ba
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::1fa80ef6403ff206ca53983cee6296fc
https://doi.org/10.1109/tc.2017.2654339
https://doi.org/10.1109/tc.2017.2654339