An enhanced approach towards improving the performance of embedding memory management units into Network-on-Chip

Autor: Debasis Behera, Suvendu Narayan Mishra, Prabodh Kumar Sahoo, Heli Amit Shah

Publikováno v: e-Prime: Advances in Electrical Engineering, Electronics and Energy, Vol 6, Iss , Pp 100332- (2023)

Network-on-Chip (NoC) initiates the design procedure of interconnection network into SoC - System-on-Chip. The current technique overcomes the drawbacks of traditional bus-based SoC, for instance, poor scalability, small-link bandwidth, and large del

Externí odkaz: https://doaj.org/article/aecd7db907644f0c93c00ce204d83230

MMNoC: Embedding Memory Management Units into Network-on-Chip for Lightweight Embedded Systems

Autor: Hyeonguk Jang, Kyuseung Han, Sukho Lee, Jae-Jin Lee, Woojoo Lee

Publikováno v: IEEE Access, Vol 7, Pp 80011-80019 (2019)

With the advent of the Internet-of-Things (IoT) era, the demand for lightweight embedded systems is rapidly increasing. So far, ultra-low power (ULP) processors have been leading the development of lightweight embedded systems. However, as the IoT er

Externí odkaz: https://doaj.org/article/95d5a865eedd4b688c19de9bd4c704c4

Tento výsledek nelze pro nepřihlášené uživatele zobrazit.
K zobrazení výsledku je třeba se přihlásit.

Online Thread and Data Mapping Using a Sharing-Aware Memory Management Unit

Autor: Matthias Diener, Philippe O. A. Navaux, Laércio Lima Pilla, Eduardo H. M. Cruz

Publikováno v: ACM Transactions on Modeling and Performance Evaluation of Computing Systems
ACM Transactions on Modeling and Performance Evaluation of Computing Systems, ACM, 2021, 5 (4), pp.1-28. ⟨10.1145/3433687⟩

Current and future architectures rely on thread-level parallelism to sustain performance growth. These architectures have introduced a complex memory hierarchy, consisting of several cores organized hierarchically with multiple cache levels and NUMA

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_dedup___::f1aa1ce169aea03d3e7609f7493f466b
https://doi.org/10.1145/3433687

Input/output virtualization of Elbrus microprocessors

Autor: N. Yu. Polyakov, S. A. Rybakov

Publikováno v: Радиопромышленность, Vol 30, Iss 3, Pp 34-39 (2020)

The article describes and compares the methods of input-output (I/O) virtualization, adapted for the Elbrus architecture. The presented methods of software emulation and paravirtualization of devices do not require hardware support and provide comple

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_dedup___::333f2d45d8905a0a0a3fde25fce32294
https://www.radioprom.org/jour/article/view/747