Zobrazeno 1 - 10
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pro vyhledávání: '"Melikyan, Vazgen"'
Akademický článek
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Autor:
Abazyan, Suren, Melikyan, Vazgen
Publikováno v:
In Microelectronics Journal October 2021 116
Publikováno v:
In Microelectronics Journal September 2016 55:26-39
Autor:
Melikyan, Vazgen Shavarsh1 vazgenm@synopsys.com, Galstyan, Vache Ashot1 vache@synopsys.com
Publikováno v:
Annual Journal of Electronics. 2015, Vol. 9, p178-181. 4p.
Autor:
V. Margaryan Hayk, Sh. Melikyan Vazgen, T. Kostanyan Harutyun, H. Musayelyan Ruben, T. Grigoryan Hayk, T. Grigoryan Mushegh, Kh. Mkhitaryan Artur, T. Kostanyan Hakob
Publikováno v:
EWDTS
In modern integrated circuits the technology scaling and supply voltages values decreasing caused degradation of noise immunity of VLSI ICs. Therefore, the rejection of the noises in the power rails become a huge challenge considering the fact of are
Publikováno v:
EWDTS
The regression test selection mechanism is represented, which leads to a decrease in the overall testing time. Provided the detailed description of the software, which selects and classifies the tests, as well as the initial results of the work done
Publikováno v:
EWDTS
A new method has been developed to obtain precise spice models of transistors that can be used in any type of research and training projects. The transistor's input and output characteristics have been received that have been compared with the charac
Autor:
H Petrosyan Oleg, V Vardanyan Hayk, Melikyan Vazgen Sh., M Avetisyan Zaven, A Ghukasyan Sevak, T Hakobyan Kimik, H. Musayelyan Ruben
Publikováno v:
2019 IEEE 39th International Conference on Electronics and Nanotechnology (ELNANO).
The estimation of reliability of schemes has a great role at verification stage of integrated circuits. Estimation of reliability includes test of scheme considering circuit aging. As a result of aging the threshold voltage of transistors changes, wh
Publikováno v:
2017 IEEE 37th International Conference on Electronics and Nanotechnology (ELNANO).
On-chip decoupling capacitors used for reducing power supply noise. In this paper, a design technique for sizing and placing on-chip decoupling cells based on circuits switching activity is proposed. Evaluation of this methods on Universal Serial Bus