Zobrazeno 1 - 10
of 20
pro vyhledávání: '"Mei-Fang Chiang"'
Autor:
Mei-Fang Chiang, 蔣梅芳
94
As technology node advances into the nanometer era, via-open defects are one of the dominant failures due to the copper cladding process. To improve via yield and reliability, redundant-via insertion is a highly recommended technique proposed
As technology node advances into the nanometer era, via-open defects are one of the dominant failures due to the copper cladding process. To improve via yield and reliability, redundant-via insertion is a highly recommended technique proposed
Externí odkaz:
http://ndltd.ncl.edu.tw/handle/98776351204977803871
Autor:
Mei-Fang Chiang, Shuangchen Li, Yiqun Wang, Yongpan Liu, Daming Zhang, Huazhong Yang, Xiaobo Sharon Hu, Baiko Sai, Xiao Sheng
Publikováno v:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 22:1491-1505
Nonvolatile (NV) processors have attracted much attention in recent years due to their zero standby power, resilience to power failures, and instant-on feature. One design challenge of NV processors is the excess area needed by NV registers. This pap
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::35cab40417366bc7db19401603996615
https://doi.org/10.1109/tvlsi.2013.2275740
https://doi.org/10.1109/tvlsi.2013.2275740
Publikováno v:
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. :2372-2379
The occurrence of via defects increases due to the shrinking size in integrated circuit manufacturing. Redundant via insertion is an effective and recommended method to reduce the yield loss caused by via failures. In this paper, we introduce the red
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::73097dc0f169cb9745c1392cbe763076
https://doi.org/10.1587/transfun.e93.a.2372
https://doi.org/10.1587/transfun.e93.a.2372
Publikováno v:
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. :1080-1087
Three-dimensional integrated circuits (3-D ICs), i.e., stacked dies, can alleviate the interconnect problem coming with the decreasing feature size and increasing integration density, and promise a solution to heterogenous integration. The vertical c
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::a1d4ec5db86b10b02790113c1869c5c5
https://doi.org/10.1587/transfun.e92.a.1080
https://doi.org/10.1587/transfun.e92.a.1080
Publikováno v:
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 27:844-857
As the technology node advances into the nanometer era, via-open defects are one of the dominant failures due to the copper cladding process. To improve via yield and reliability, redundant-via insertion is a highly recommended technique proposed by
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::f35ef639a55ff5b40b5e3e7dd66e613b
https://doi.org/10.1109/tcad.2008.917597
https://doi.org/10.1109/tcad.2008.917597
Autor:
Yiqun Wang, Yanxin Yan, Huazhong Yang, Bo Zhao, Baiko Sai, Daming Zhang, Yongpan Liu, Mei-Fang Chiang, Shuangchen Li
Publikováno v:
ESSCIRC
Nonvolatile processors offer a number of desirable properties including instant on/off, zero standby power and resilience to power failures. This paper presents a fabricated nonvolatile processor based on ferroelectric flip-flops. These flipflops are
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::8bd2b6e3c57c8afb2eac9ae3649af776
https://doi.org/10.1109/esscirc.2012.6341281
https://doi.org/10.1109/esscirc.2012.6341281
Autor:
null Yiqun Wang, null Yongpan Liu, null Yumeng Liu, null Daming Zhang, null Shuangchen Li, null Baiko Sai, null Mei-Fang Chiang, null Huazhong Yang
Publikováno v:
2012 Design, Automation & Test in Europe Conference & Exhibition (DATE).
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::3c47848770a43e7e79356d6bee6645f7
https://doi.org/10.1109/date.2012.6176714
https://doi.org/10.1109/date.2012.6176714
Publikováno v:
2009 IEEE 8th International Conference on ASIC.
The occurrence of via defects increases due to the shrinking size in integrated circuit manufacturing. Redundant via insertion is an effective and recommended method to reduce the yield loss caused by via failures. In this paper, we introduce a redun
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::06bd6a650402bc03e210f5273ff8b8b5
https://doi.org/10.1109/asicon.2009.5351310
https://doi.org/10.1109/asicon.2009.5351310
Publikováno v:
2009 IEEE 8th International Conference on ASIC.
As VLSI design complexity continues to increase, the yield loss due to via failure becomes more and more significant. Redundant via insertion is highly recommended for improving chip yield and reliability. In this paper, we study the redundant via in
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::17463455a01f4850a02562b4b1e6a7c6
https://doi.org/10.1109/asicon.2009.5351227
https://doi.org/10.1109/asicon.2009.5351227
Publikováno v:
2009 Design, Automation & Test in Europe Conference & Exhibition.
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::016ea44ac68c2157927f753b56f25bcb
https://doi.org/10.1109/date.2009.5090895
https://doi.org/10.1109/date.2009.5090895