Zobrazeno 1 - 8
of 8
pro vyhledávání: '"Mehdi Khanpour"'
Autor:
Afshin Momtaz, Bo Zhang, Adesh Garg, Mahmoud Reza Ahmadi, Ali Nazemi, Namik Kocaman, Heng Zhang, Jun Cao, Mehdi Khanpour
Publikováno v:
IEEE Journal of Solid-State Circuits. 50:426-439
This paper presents the design of a power- and area-efficient, high-performance dual-path receiver analog front-end (AFE) for wide multistandard applications of 8.5–11.5 Gb/s, such as 10GBASE-LRM, 10GBASE-KR, 10GBASE-CX1, and 10GBASE-LR/SR. A commo
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::3eacdc86408645dd693b131f0c2fa0da
https://doi.org/10.1109/jssc.2014.2364032
https://doi.org/10.1109/jssc.2014.2364032
Autor:
Mehdi Khanpour, Shiwei Sheng, Afshin Momtaz, Delong Cui, Tim He, Ali Nazemi, Tamer Ali, Heng Zhang, Burak Catli, Ben Rhew, Yonghyun Shim, Jun Cao, Guansheng Li, Bo Zhang, Kangmin Hu, Hairong Yu
Publikováno v:
ISSCC
At rates of 100Gb/s and above, CMOS DSP-based transceivers integrated with high-sampling-rate data converters are critical to realize the phase-sensitive modulation schemes based on coherent detection that are essential to metro and long-haul network
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::6c25c19f23393122e6a875f58496d31d
https://doi.org/10.1109/isscc.2017.7870472
https://doi.org/10.1109/isscc.2017.7870472
Autor:
Siavash Fallahi, Mehdi Khanpour, Ali Nazemi, Namik Kocaman, Afshin Momtaz, Mahyar Kargar, Ullas Singh
Publikováno v:
IEEE Journal of Solid-State Circuits. 48:1875-1884
An 8.5-11.5-Gbps SONET transceiver with referenceless clock and data recovery (CDR) employing an algorithmic frequency acquisition scheme is presented. Without any training sequence, the frequency acquisition algorithm utilizes a modified digital qua
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::2d86fc264ecece61b1252ac306af7f25
https://doi.org/10.1109/jssc.2013.2259033
https://doi.org/10.1109/jssc.2013.2259033
Autor:
Afshin Momtaz, Hassan Maarefi, Deyi Pi, Bo Zhang, Wei Zhang, Delong Cui, Bharath Raghavan, Nick Huang, Mehdi Khanpour, Tamer Ali, Anand Vasani, Zhi Huang, Ali Nazemi, Ullas Singh, Jun Cao
Publikováno v:
IEEE Journal of Solid-State Circuits. 47:3249-3260
This paper describes a dual-channel 23 (20 to 27) Gbps chipset designed in a 40-nm CMOS process for 40 Gbps differential quadrature phase-shift keying (DQPSK) optical transmission. The transmitter has a 2-tap FIR filter and generates two channels of
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::a79a0d2b24b1985db0a2b57b93c5693d
https://doi.org/10.1109/jssc.2012.2216451
https://doi.org/10.1109/jssc.2012.2216451
Autor:
Bo Zhang, Namik Kocaman, Jun Cao, Ali Nazemi, Mehdi Khanpour, Afshin Momtaz, Mahmoud Reza Ahmadi, Adesh Garg, Heng Zhang
Publikováno v:
ISSCC
Demand for bandwidth in metro networks and data centers has fueled the deployment of 10Gb/s traffic over legacy data links, such as backplanes (KR) and multimode fiber (MMF) [1]. Under severe channel impairments, an ADC-based receiver with a DSP back
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::69024dbdf8be8e8e3b24692017ce54c0
https://doi.org/10.1109/isscc.2013.6487625
https://doi.org/10.1109/isscc.2013.6487625
Publikováno v:
CICC
An 8.5–11.5Gbps SONET transceiver with a referenceless CDR employing an algorithmic frequency acquisition scheme (without using any training sequence) is designed in a 65nm digital CMOS process. A modified digital quadricorrelator frequency detecto
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::925f6a641c09b616b630953c9f951f09
https://doi.org/10.1109/cicc.2012.6330578
https://doi.org/10.1109/cicc.2012.6330578
Autor:
Afshin Momtaz, Bo Zhang, Jun Cao, Mehdi Khanpour, Deyi Pi, Anand Vasani, Hassan Maarefi, Zhi Huang, Delong Cui, Bharath Raghavan, Ali Nazemi, Wei Zhang, Tamer Ali, Ullas Singh, Nick Huang
Publikováno v:
ISSCC
Recently developed 40Gb/s optical modulation formats such as return-to-zero differential quadrature phase-shift keying (RZ-DQPSK) and carrier-suppressed return-to-zero differential quadrature phase-shift keying (CS-RZ-DQPSK) are promising, since they
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::99a22d135fff4c41b387be1cbfeae90a
https://doi.org/10.1109/isscc.2012.6177006
https://doi.org/10.1109/isscc.2012.6177006
Publikováno v:
2009 IEEE MTT-S International Microwave Symposium Digest.
A low-loss source-pull tuner network consisting of transmission lines and CMOS switches is integrated on the same chip with a W-band LNA in 65nm RF CMOS technology, allowing for the accurate characterization of the optimal noise impedance of n-MOSFET
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::4505ebc56d8e5d3ca4d1715ea4471e42
https://doi.org/10.1109/mwsym.2009.5165811
https://doi.org/10.1109/mwsym.2009.5165811