A Robust Ultra-Low Voltage CPU Utilizing Timing-Error Prevention

Autor: Markus Hiienkari, Jukka Teittinen, Lauri Koskinen, Matthew Turnquist, Jani Mäkipää, Arto Rantala, Matti Sopanen, Mikko Kaltiokallio

Publikováno v: Journal of Low Power Electronics and Applications, Vol 5, Iss 2, Pp 57-68 (2015)

To minimize energy consumption of a digital circuit, logic can be operated at sub- or near-threshold voltage. Operation at this region is challenging due to device and environment variations, and resulting performance may not be adequate to all appli

Externí odkaz: https://doaj.org/article/c1af18f6b459465a89636a8763954d5c

Ultra-wide voltage range 32-bit RISC CPU with timing-error prevention in 28nm CMOS

Autor: Markus Hiienkari, Mikko Kaltiokallio, Arto Rantala, Matti Sopanen, Jukka Teittinen, Lauri Koskinen, Matthew Turnquist, Jani Makipaa

Publikováno v: Hiienkari, M, Teittinen, J, Koskinen, L, Turnquist, M, Kaltiokallio, M, Mäkipää, J, Rantala, A & Sopanen, M 2014, Ultra-wide voltage range 32-bit RISC CPU with timing-error prevention in 28nm CMOS . in Proceedings : SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2014 ., 7028192, IEEE Institute of Electrical and Electronic Engineers, IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2014, Millbrae, CA, United Kingdom, 6/10/14 . https://doi.org/10.1109/S3S.2014.7028192

To minimize energy consumption of a digital circuit, logic can be operated at sub- or near-threshold voltage. Operation at this region is challenging due to device and environment variations, and resulting performance may not be adequate to all appli

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_dedup___::971a004791ac588534123e7c3c0e8bdc
https://cris.vtt.fi/en/publications/b29dd3c0-5088-47be-a364-c15053d1cdda

Implementation experiments of analog nonvolatile memory with a standard 0.35 μm CMOS

Autor: Matti Sopanen, Markku Åberg, Arto Rantala

Publikováno v: Rantala, A, Sopanen, M & Åberg, M 2004, Implementation experiments of analog nonvolatile memory with a standard 0.35 μm CMOS . in Proceedings of the 22nd Norchip Conference 2004 . IEEE Institute of Electrical and Electronic Engineers, pp. 71-74, 22nd NORCHIP Conference, Oslo, Norway, 8/11/04 . https://doi.org/10.1109/NORCHP.2004.1423825

This paper presents a study upon implementation of a nonvolatile memory with a standard CMOS process. The main emphasis is to obtain an analog, continuous value, EEPROM module. The accuracy, reliability and reproducibility performance of the differen

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_dedup___::fc0354a0b9e2718339b209e54d0395a3
https://doi.org/10.1109/norchp.2004.1423825