Zobrazeno 1 - 10
of 70
pro vyhledávání: '"Matthias Passlack"'
Autor:
Hsin‐Yuan Chiu, Tzu‐Ang Chao, Nathaniel S. Safron, Sheng‐Kai Su, San‐Lin Liew, Wei‐Sheng Yun, Po‐Sen Mao, Yu‐Tung Lin, Vincent Duen‐Huei Hou, Tung‐Ying Lee, Wen‐Hao Chang, Matthias Passlack, Hon‐Sum Philip Wong, Iuliana P. Radu, Han Wang, Gregory Pitner, Chao‐Hsin Chien
Publikováno v:
Advanced Electronic Materials, Vol 10, Iss 3, Pp n/a-n/a (2024)
Abstract Carbon nanotube (CNT) field effect transistors (CNFETs) show promise for the next generation VLSI systems due to their excellent scalability, energy efficiency, and speed. However, high leakage current is a drawback of large diameter CNTs (d
Externí odkaz:
https://doaj.org/article/262eb55fe9514f40947d0b2bde04564a
Publikováno v:
IEEE Journal of the Electron Devices Society, Vol 7, Pp 88-99 (2019)
Using a tight-binding mode-space NEGF technique, we explore the essential physics, design and performance potential of the III-V core-shell (CS) nanowire (NW) heterojunction tunneling field-effect transistor (TFET). The CS TFET “line-tunneling” c
Externí odkaz:
https://doaj.org/article/3dccccb856c947f7b09ae83ffd955ff2
Autor:
Gerben Doornbos, Martin Holland, Georgios Vellianitis, Mark J. H. Van Dal, Blandine Duriez, Richard Oxland, Aryan Afzalian, Ta-Kun Chen, Gordon Hsieh, Matthias Passlack, Yee-Chia Yeo
Publikováno v:
IEEE Journal of the Electron Devices Society, Vol 4, Iss 5, Pp 253-259 (2016)
We report on the first realization of InAs n-channel gate-all-around nanowire MOSFETs on 300 mm Si substrates using a fully very large-scale integration (VLSI)-compatible flow. Scaling of the equivalent oxide thickness EOT in conjunction with high-κ
Externí odkaz:
https://doaj.org/article/3f9a947ff28244ed8ba1c54803efcb7e
Autor:
Qing Lin, Gregory Pitner, Carlo Gilardi, Sheng-Kai Su, Zichen Zhang, Edward Chen, Prabhakar Bandaru, Andrew Kummel, Han Wang, Matthias Passlack, Subhasish Mitra, H.-S. Philip Wong
Publikováno v:
IEEE Electron Device Letters. 43:490-493
Autor:
Nujhat Tasneem, Muhammad M. Islam, Zheng Wang, Zijian Zhao, Navnidhi Upadhyay, Sarah F. Lombardo, Hang Chen, Jae Hur, Dina Triyoso, Steven Consiglio, Kanda Tapily, Robert Clark, Gert Leusink, Santosh Kurinec, Suman Datta, Shimeng Yu, Kai Ni, Matthias Passlack, Winston Chern, Asif Khan
Publikováno v:
IEEE Transactions on Electron Devices. 69:1568-1574
Autor:
Zichen Zhang, Matthias Passlack, Gregory Pitner, Cheng-Hsuan Kuo, Scott T. Ueda, James Huang, Harshil Kashyap, Victor Wang, Jacob Spiegelman, Kai-Tak Lam, Yu-Chia Liang, San Lin Liew, Chen-Feng Hsu, Andrew C. Kummel, Prabhakar Bandaru
Publikováno v:
ACS Applied Materials & Interfaces. 14:11873-11882
A new generation of compact and high-speed electronic devices, based on carbon, would be enabled through the development of robust gate oxides with sub-nanometer effective oxide thickness (EOT) on carbon nanotubes or graphene nanoribbons. However, to
Autor:
Fei Huang, Matthias Passlack, San Lin Liew, Zhouchangwan Yu, Qing Lin, Aein Babadi, Vincent D.-H. Hou, Paul C. McIntyre, S. Simon Wong
Publikováno v:
IEEE Electron Device Letters. 43:212-215
Autor:
Peter Ramvall, A. Devin Giddings, Yee-Chia Yeo, Aryan Afzalian, Ruey-Lian Hwang, T. Vasen, Matthias Passlack
Publikováno v:
ACS Applied Nano Materials. 2:1253-1258
Growth of ultrathin semiconducting nanowires (NWs) and incorporation of dopants suitable for future CMOS scaling targets (diameter
Autor:
C. Kuo, Lain-Jong Li, Prabhakar R. Bandaru, Matthias Passlack, H. Kashyap, Subhasish Mitra, Z. Zhang, Jin Cai, H-S Philip Wong, Andrew C. Kummel, T. Weiss, S.-K Su, Gregory Pitner, Q. Lin, Zhiping Yu, C. Gilardi, T. A. Chao
Publikováno v:
2020 IEEE International Electron Devices Meeting (IEDM).
To realize superior electrostatic control, a gate oxide bilayer for carbon nanotubes (CNT) is employed consisting of a 0.35 nm interfacial dielectric (k=7.8) and 2.5 nm high-k ALD dielectric (k=24). Using experimentally measured dielectric constants
Autor:
Martin Christopher Holland, Matthias Passlack, Yee-Chia Yeo, Peter Ramvall, Stephen Thoms, I.G. Thayne, T. Vasen, Douglas Macintyre, R. Droopad, Shyh-Wei Wang, R. Contreras-Guerrero, J.S. Rojas-Ramirez, Richard Kenneth Oxland, Xu Li, Gerben Doornbos, Carlos H. Diaz, Chang Yen-An, S. W. Chang
Publikováno v:
IEEE Electron Device Letters. 37:261-264
We report the first demonstration of InAs FinFETs with fin width $\textrm {W}_{{\mathrm{fin}}}$ in the range 25–35 nm, formed by inductively coupled plasma etching. The channel comprises defect-free, lattice-matched InAs with fin height $\textrm {H