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Autor:
Richard Langlois, Christy S. Tyberg, Ray Robertazzi, Pascale Gagnon, Katsuyuki Sakuma, Christian Bergeron, Michael Scheurmann, Stephane Barbeau, Steve Whitehead, Matthew Wordeman
Publikováno v:
2017 IEEE 67th Electronic Components and Technology Conference (ECTC).
3D multi-layer chip stacking is a significant assembly challenge with dependencies on die size and thickness, interconnect pitch, bump diameter, number of dies involved, and die warpage. The assembly processes used to overcome the technical difficult
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::f68fda94bdd8009594878bd4d1c59cbc
https://doi.org/10.1109/ectc.2017.53
https://doi.org/10.1109/ectc.2017.53
