Zobrazeno 1 - 10
of 30
pro vyhledávání: '"Matthew V. Metz"'
Autor:
Carl H. Naylor, Chelsey Dorow, O'brien Kevin P, Kirby Maxey, Arnab Sen Gupta, Andy Hsiao, Tronic Tristan A, Penumatcha Ashish Verma, Scott B. Clendenning, Gosavi Tanay, Matthew V. Metz, Michael Christenson, Sudarat Lee, Robert L. Bristol, Uygar E. Avci, Alaan Urusa, A. A. Oni, Hui Zhu
Publikováno v:
IEEE Transactions on Electron Devices. 68:6592-6598
2-D-material channels enable ultimate scaling of MOSFET transistors and will help Moore's Law scaling for years. We demonstrate the state of both n- and p-MOSFETs using monolayer transition metal dichalcogenide (TMD) channels of sub-1 nm thickness an
Autor:
Manan Mehta, Merrill Devin, S. Ghose, X. Weng, H. Li, Anand Portland Murthy, Ashish Agrawal, Jessica M. Torres, Matthew V. Metz, A. A. Oni, S. Vishwanath, Chouksey Siddharth, Jack Portland Kavalieros, W. Rachmady
Publikováno v:
2020 IEEE International Electron Devices Meeting (IEDM).
For the first time, we report a short channel high performance, gate-all-around strained Si 0.4 Ge 0.6 nanosheet PMOSFET with aggressively scaled dimensions. We demonstrate realization of s-Si 0.4 Ge 0.6 nanosheet with 5nm thickness and device with L
Autor:
Prashant Majhi, Le Van H, Tung I-Cheng, Brian S. Doyle, Yoo Hui Jae, Tobias L Brown-Heft, Yu-Jin Chen, Abhishek Sharma, Miriam Reshotko, Jack T. Kavalieros, Matthew V. Metz
Publikováno v:
2020 IEEE International Electron Devices Meeting (IEDM).
Scaled ferroelectric transistors (L g =76 nm) in a back- gated configuration are fabricated with a channel-last process flow. Using this approach, optimization of the ferroelectric gate oxide film can be decoupled from that of the semiconductor chann
Autor:
W. Rachmady, Phan Anh, G. Dewey, P. Nguyen, Matthew V. Metz, Tung I-Cheng, Patrick Morrow, Rajat Kanti Paul, Scott B. Clendenning, Nicole K. Thomas, A. A. Oni, Ryan Keech, Marko Radosavljevic, Huang Cheng-Ying, Alaan Urusa, Manan Mehta, Kang Jun Sung, A. Lilak, Mannebach Ehren, Hui Jae Yoo, Bob Turkot, Kabir Nafees, S. Vishwanath, K. L. Cheong, Richard E. Schenker, B. Krist, Michael K. Harper, Jack Portland Kavalieros
Publikováno v:
2020 IEEE International Electron Devices Meeting (IEDM).
We demonstrate 3-D self-aligned stacked NMOS-on-PMOS multiple Si nanoribbon transistors with successful integration of vertically stacked dual source/drain EPI process and vertically stacked dual metal gate process. Both top NMOS and bottom PMOS show
Autor:
Matthew V. Metz, James S. Clarke, Mauro J. Kobrinsky, J. Bielefeld, Ramanan V. Chebiam, Marius K. Orlowski, Sean W. King, Carl H. Naylor, S. Vyas, John J. Plombon, R. Thapa, Vamseedhara Vemuri, James M. Blackwell, Ye Fan, David J. Michalak, Florian Gstrein, Nicholas C. Strandwitz, Michelle M. Paquette
Publikováno v:
2020 IEEE International Electron Devices Meeting (IEDM).
The remarkable advancement of CMOS electronics over the past two decades has been greatly aided by innovations allowing dielectric scaling across both ends of the permittivity spectrum. This paper describes how new dielectric innovations beyond permi
Autor:
W. Rachmady, Ashish Agrawal, Huang Cheng-Ying, B. Krist, Matthew V. Metz, Chouksey Siddharth, Jack Portland Kavalieros, A. A. Oni, Jessica M. Torres, Kimin Jun, Rajat Kanti Paul, Seung Hoon Sung, Hui Jae Yoo, T. Talukdar, G. Elbaz, Wong Lawrence D, Mueller Brennen, Robert B. Turkot, Fischer Paul B, P. Sears, Benjamin Chu-Kung, G. Dewey, Phan Anh, T. Michaelos
Publikováno v:
2019 IEEE International Electron Devices Meeting (IEDM).
We report a short channel high performance Ge PMOS integrated with Si NMOS in sequential monolithic 3D stacking. A layer transfer Ge PMOS with record I ON = 497 μA/μm at I OFF = 8nA/μm and I ON = 630 μA/μm at I OFF = 100nA/μm and V DS = -0.5V i
Autor:
Fatih Hamzaoglu, C. English, Tahir Ghani, Matthew V. Metz, Joodong Park, Pedro A. Quintero, M. Seth, M. Sekhar, Kevin J. Fischer, Seghete Dragos, Ilya V. Karpov, Christopher J. Jezewski, Yao-Feng Chang, P. Bai, Nilanjan Das, Ouellette Daniel G, J. O'Donnell, A. Pirkle, M. Bohr, Pulkit Jain, Umut Arslan, James S. Clarke, A. Sen Gupta, A. Chaudhari, Albert Chen, Blake C. Lin, O. Baykan, Oleg Golonzka, Christopher J. Wiegand, Chris Connor, Roza Kotlyar, Hui Jae Yoo, Nathan L. Strutt, P. Hentges, H. Kothari
Publikováno v:
2019 Symposium on VLSI Technology.
This paper presents key specifications of RRAM-based nonvolatile memory embedded into Intel 22FFL FinFET Technology. 22FFL is a high performance, ultra low power technology developed for mobile and RF applications providing extensive high voltage and
Autor:
Roza Kotlyar, Payam Amin, Lieven M. K. Vandersypen, Singh Kanwaljit, Jessica M. Torres, G. Droulers, Matthew V. Metz, GertJan Eenink, R. Li, R. Pillarisetty, A. M. J. Zwerver, Thomas F. Watson, Nicole K. Thomas, Juan Pablo Dehollain, Jeanette M. Roberts, L. Massa, Christian Volk, Nodar Samkharadze, Menno Veldhorst, G. Zheng, J.M. Boter, Giordano Scappucci, D. Sabbagh, Lester Lampert, Patrick H. Keys, Brian Paquelet Wuetz, Hubert C. George, James S. Clarke
Publikováno v:
2018 IEEE International Electron Devices Meeting, IEDM 2018, 2018-December
Quantum computing's value proposition of an exponential speedup in computing power for certain applications has propelled a vast array of research across the globe. While several different physical implementations of device level qubits are being inv
Autor:
Matthew V. Metz, Robert S. Chau, B. Jin, Marko Radosavljevic, Brian S. Doyle, Gilbert Dewey, Amlan Majumdar, Mark L. Doczy, Suman Datta, Justin K. Brask, Jack T. Kavalieros
Publikováno v:
Microelectronic Engineering. 80:1-6
High-k gate dielectrics and metal gate electrodes are required for enabling continued equivalent gate oxide thickness scaling, and hence high performance, and for controlling gate oxide leakage for both future silicon and emerging nonsilicon nanoelec
Autor:
Scott Hareland, Brian S. Doyle, Jack T. Kavalieros, Matthew V. Metz, Suman Datta, Mark L. Doczy, B. Jin, Boyan Boyanov, Robert S. Chau
Publikováno v:
Physica E: Low-dimensional Systems and Nanostructures. 19:1-5
Silicon transistors have undergone rapid miniaturization in the past several decades. Recently reported CMOS devices have dimensional scales approaching the “nano-transistor” regime. This paper discusses performance characteristics of a MOSFET de