Zobrazeno 1 - 4
of 4
pro vyhledávání: '"Matthew D. Moon"'
Publikováno v:
25th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC 2014).
Backside roughness variation on incoming Silicon-On-Insulator (SOI) wafers can cause systematic variations in the dimensions of Al interconnects. Wafers with more backside roughness are more effectively cooled during reactive ion etching (RIE), resul
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::c9523ecde4be85b13447ccdbb0c63285
https://doi.org/10.1109/asmc.2014.6846960
https://doi.org/10.1109/asmc.2014.6846960
Autor:
Shawn A. Adderly, Matthew D. Moon, Anthony C. Speranza, David C. Thomas, Nathaniel W. Bowe, Timothy D. Sullivan, Jeffrey P. Gambino
Publikováno v:
ASMC 2013 SEMI Advanced Semiconductor Manufacturing Conference.
Extrusions are a well-known phenomenon in Al interconnect stacks. We review experimental approaches to mitigate extrusions including depositing a low temperature oxide (LTO) on the film stack, modulation of the metal anneal conditions, and moving the
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::ab2fde6797d494b61f1c88c68c8b3f55
https://doi.org/10.1109/asmc.2013.6552794
https://doi.org/10.1109/asmc.2013.6552794
Autor:
Timothy D. Sullivan, Shawn A. Adderly, Jeffrey P. Gambino, Max L. Lifson, Matthew D. Moon, Nathaniel W. Bowe
Publikováno v:
2013 IEEE Conference on Reliability Science for Advanced Materials and Devices.
Vias are formed in interconnect structures using a polymerizing chemistry in order to avoid etching the underlying metal wires. However, a drawback of the polymerizing chemistry is that etch residues can remain in the via opening, resulting in high v
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::193aef0b0c7681cc7f5591dd4ef6d282
https://doi.org/10.1109/rsamd.2013.6647898
https://doi.org/10.1109/rsamd.2013.6647898
Autor:
M. Gordon, S. St Onge, Edward J. Gordon, Hanyi Ding, Alvin J. Joseph, Matthew D. Moon, Mete Erturk, J. Dunn, A.K. Stamper, Z.X. He, Ebenezer E. Eshun, Douglas M. Daley, Douglas D. Coolbaugh
Publikováno v:
2007 Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems.
High quality factor inductors and highly matched low capacitance density horizontal parallel plate metal-insulator-metal capacitors were fabricated in 130nm RF-CMOS technology with minimal or zero processing step addition. The high quality factor ind
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::25df62b04df9c968041218ff5fb1bd4b
https://doi.org/10.1109/smic.2007.322791
https://doi.org/10.1109/smic.2007.322791