Zobrazeno 1 - 10
of 253
pro vyhledávání: '"Matrix clock"'
Autor:
Vaibbhav Taraate
Publikováno v:
Digital Logic Design Using Verilog ISBN: 9789811631986
Digital Logic Design Using Verilog ISBN: 9788132227892
Digital Logic Design Using Verilog ISBN: 9788132227892
In the practical ASIC and SOC designs the multiple clocks are used and the designs are called as multiple clock domain designs. These kinds of designs need to be described using the efficient design architectures and Verilog RTL. This chapter focuses
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::cce9f9d114b2da6d389be8202bbf3127
https://doi.org/10.1007/978-981-16-3199-3_22
https://doi.org/10.1007/978-981-16-3199-3_22
Publikováno v:
NCA
After the seminal paper by L. Lamport, which introduced (scalar) logical clocks, several other data structures for keeping track of causality in distributed systems have been proposed, including vector and matrix clocks. These are able to capture cau
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::a866f0de05963765bac3bf7d115fafd0
https://doi.org/10.1109/nca51143.2020.9306734
https://doi.org/10.1109/nca51143.2020.9306734
Publikováno v:
IEEE Transactions on Automatic Control. 63:1708-1723
This paper studies the impact of clock mismatches and quantization on networked control systems. We consider a scenario where the plant's state is measured by a sensor that communicates with the controller through a network. Variable communication de
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::73d2024498587143ca289bb139be47a3
https://doi.org/10.1109/tac.2017.2753938
https://doi.org/10.1109/tac.2017.2753938
Autor:
Punit Gupta, Ravi Shankar Jha
Publikováno v:
Wireless Personal Communications. 97:6469-6481
The Internet of Things is a trending future technological revolution that emerging distributed computing and real-time based application and its development depends on dynamic technical innovation in a number of important fields from wireless sensors
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::e2d80cb7e743c28d8a12a0fb593f6c87
https://doi.org/10.1007/s11277-017-4848-1
https://doi.org/10.1007/s11277-017-4848-1
Publikováno v:
IEEE Communications Letters. 21:1277-1280
The aim of this letter is to improve the performance of clock synchronization in EtherCAT networks. Although EtherCAT synchronizes the slave clocks to the reference clock using a distributed clock synchronization mechanism, a synchronization error st
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::6a53030cba3f67064b0c26db49c153dc
https://doi.org/10.1109/lcomm.2017.2668400
https://doi.org/10.1109/lcomm.2017.2668400
Publikováno v:
IEEE Transactions on Signal Processing. 65:2714-2724
Time synchronization is crucial for wireless sensor networks (WSNs) since it maintains data consistency, coordination, and enables other fundamental operations. Over the last decade, a number of powerful time synchronization algorithms have been prop
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::37c21f4ffec51e43a95c895198805868
https://doi.org/10.1109/tsp.2017.2675863
https://doi.org/10.1109/tsp.2017.2675863
Publikováno v:
Chinese Astronomy and Astrophysics. 41:263-281
Time synchronization plays an important role in the spacecraft formation flight and constellation autonomous navigation, etc. For the application of clock synchronization in a network system, it is not always true that all the observed nodes in the n
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::d9a580a238d95d07562f0bb249af423f
https://doi.org/10.1016/j.chinastron.2017.04.008
https://doi.org/10.1016/j.chinastron.2017.04.008
Publikováno v:
IEEE Transactions on Wireless Communications. 16:771-783
Timestamp free clock synchronization in a master–slave network, i.e., synchronization where no timestamps are exchanged between the nodes, is considered. For highly accurate synchronization, a novel discrete-valued clock model is introduced. It is
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::005d11eb813c1ceddd1ac662f844d73f
https://doi.org/10.1109/twc.2016.2630063
https://doi.org/10.1109/twc.2016.2630063
Autor:
Rickard Ewetz, Cheng-Kok Koh
Publikováno v:
Integration. 56:115-127
Clock networks are required to be constructed with adequate safety margins in the skew constraints to operate correctly even under the influence of variations. In this work, a scalable clock scheduler is developed to drive a synthesis framework that
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::286301a79f2b37528adc96e281a39c96
https://doi.org/10.1016/j.vlsi.2016.10.012
https://doi.org/10.1016/j.vlsi.2016.10.012
Publikováno v:
SPAA
We argue that grid structures are a very promising alternative to the standard approach for distributing a clock signal throughout VLSI circuits and other hardware devices. Traditionally, this is accomplished by a delay-balanced clock tree, which dis
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::e921313a88d93b865b6441d8afc4abb3