Zobrazeno 1 - 10
of 500
pro vyhledávání: '"Mateo Valero"'
Publikováno v:
International Journal of Distributed Sensor Networks, Vol 11 (2015)
Big data processing is becoming a reality in numerous real-world applications. With the emergence of new data intensive technologies and increasing amounts of data, new computing concepts are needed. The integration of big data producing technologies
Externí odkaz:
https://doaj.org/article/7414824972dd486c90b78316906b3197
Autor:
Lazo, Cristóbal Ramírez, Reggiani, Enrico, Morales, Carlos Rojas, Bagué, Roger Figueras, Vargas, Luis Alfonso Villa, Salinas, Marco Antonio Ramírez, Cortés, Mateo Valero, Unsal, Osman Sabri, Cristal, Adrián
Modern scientific applications are getting more diverse, and the vector lengths in those applications vary widely. Contemporary Vector Processors (VPs) are designed either for short vector lengths, e.g., Fujitsu A64FX with 512-bit ARM SVE vector supp
Externí odkaz:
http://arxiv.org/abs/2111.05301
Autor:
Francesco Minervini, Oscar Palomar, Osman Unsal, Enrico Reggiani, Josue Quiroga, Joan Marimon, Carlos Rojas, Roger Figueras, Abraham Ruiz, Alberto Gonzalez, Jonnatan Mendoza, Ivan Vargas, César Hernandez, Joan Cabre, Lina Khoirunisya, Mustapha Bouhali, Julian Pavon, Francesc Moll, Mauro Olivieri, Mario Kovac, Mate Kovac, Leon Dragic, Mateo Valero, Adrian Cristal
Publikováno v:
ACM Transactions on Architecture and Code Optimization. 20:1-25
The maturity level of RISC-V and the availability of domain-specific instruction set extensions, like vector processing, make RISC-V a good candidate for supporting the integration of specialized hardware in processor cores for the High Performance C
Autor:
Guillem Cabo, Gerard Candon, Xavier Carril, Max Doblas, Marc Dominguez, Alberto Gonzalez, Cesar Hernandez, Victor Jimenez, Vatistas Kostalampros, Ruben Langarita, Neiel Leyva, Guillem Lopez-Paradis, Jonnatan Mendoza, Francesco Minervini, Julian Pavon, Cristobal Ramirez, Narcis Rodas, Enrico Reggiani, Mario Rodriguez, Carlos Rojas, Abraham Ruiz, Victor Soria, Alejandro Suanes, Ivan Vargas, Roger Figueras, Pau Fontova, Joan Marimon, Victor Montabes, Adrian Cristal, Carles Hernandez, Ricardo Martinez, Miquel Moreto, Francesc Moll, Oscar Palomar, Marco A. Ramirez, Antonio Rubio, Jordi Sacristan, Francesc Serra-Graells, Nehir Sonmez, Lluis Teres, Osman Unsal, Mateo Valero, Luis Villa
Publikováno v:
2022 37th Conference on Design of Circuits and Integrated Circuits (DCIS).
This paper describes the design, verification, implementation and fabrication of the Drac Vector IN-Order (DVINO) processor, a RISC-V vector processor capable of booting Linux jointly developed by BSC, CIC-IPN, IMB-CNM (CSIC), and UPC. The DVINO proc
Autor:
Cristobal Ramirez Lazo, Enrico Reggiani, Carlos Rojas Morales, Roger Figueras Bague, Luis A. Villa Vargas, Marco A. Ramirez Salinas, Mateo Valero Cortes, Osman Sabri Unsal, Adrian Cristal
Publikováno v:
UPCommons. Portal del coneixement obert de la UPC
Universitat Politècnica de Catalunya (UPC)
Universitat Politècnica de Catalunya (UPC)
Modern scientific applications are getting more diverse, and the vector lengths in those applications vary widely. Contemporary Vector Processors (VPs) are designed either for short vector lengths, e.g., Fujitsu A64FX with 512-bit ARM SVE vector supp
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::61ae05aa8bd5a43262b6dc365777a7b9
Autor:
Rosa M. Badia, Miquel Moreto, Marc Casas, Kallia Chronaki, Mateo Valero, Alejandro Rico, Eduard Ayguadé
Publikováno v:
Journal of Parallel and Distributed Computing
Recercat. Dipósit de la Recerca de Catalunya
instname
UPCommons. Portal del coneixement obert de la UPC
Universitat Politècnica de Catalunya (UPC)
Digital.CSIC. Repositorio Institucional del CSIC
Recercat. Dipósit de la Recerca de Catalunya
instname
UPCommons. Portal del coneixement obert de la UPC
Universitat Politècnica de Catalunya (UPC)
Digital.CSIC. Repositorio Institucional del CSIC
Asymmetric multi-cores (AMCs) are a successful architectural solution for both mobile devices and supercomputers. By maintaining two types of cores (fast and slow) AMCs are able to provide high performance under the facility power budget. This paper
Publikováno v:
UPCommons. Portal del coneixement obert de la UPC
Universitat Politècnica de Catalunya (UPC)
Universitat Politècnica de Catalunya (UPC)
Moore’s Law predicted that the number of transistors on a chip would double approximately every 2 years. However, this trend is arriving at an impasse. Optimizing the usage of the available transistors within the thermal dissipation capabilities of
Autor:
Miljan Djordjevic, Ivan Ratkovic, Kristy Yoshimoto, Mateo Valero, Nenad Korolija, Milos Kotlar, Veljko Milutinovic
This chapter starts from the assumption that near future 100BTransistor SuperComputers-on-a-Chip will include N big multi-core processors, 1000N small many-core processors, a TPU-like fixed-structure systolic array accelerator for the most frequently
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::de80bc6d98352355d375bdeaff255b95
https://doi.org/10.4018/978-1-7998-7156-9.ch021
https://doi.org/10.4018/978-1-7998-7156-9.ch021
Publikováno v:
UPCommons. Portal del coneixement obert de la UPC
Universitat Politècnica de Catalunya (UPC)
Euro-Par 2021: Parallel Processing ISBN: 9783030856649
Euro-Par
Universitat Politècnica de Catalunya (UPC)
Euro-Par 2021: Parallel Processing ISBN: 9783030856649
Euro-Par
The ever-increasing gap between the processor and main memory speeds requires careful utilization of the limited memory link. This is additionally emphasized for the case of memory-bound applications. Prioritization of memory requests in the memory c
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::667097fe8e6ae7cec2ccedab98299577
Autor:
Jelena Skorucak, Erfan Sadeqi Azer, Erich J. Neuhold, Massimo De Santo, Miljan Djordjevic, Laura Dipietro, Miroslav Kosanic, Stevan Stankovic, Milos Kotlar, Zoran Babovic, Kristy Yoshimoto, Ivan Ratkovic, Mateo Valero, Nenad Korolija, Miroslav Bojovic, Bozidar Miladinovic, Akira Tsuda, Gerhard Klimeck, Nenad Filipovic, Veljko Milutinovic
Publikováno v:
UPCommons. Portal del coneixement obert de la UPC
Universitat Politècnica de Catalunya (UPC)
MECO
Universitat Politècnica de Catalunya (UPC)
MECO
This paper introduces a conceptual 100BillionTransistor (100BT) SuperComputers-on-a-Chip consisting of N big multi-core processors, 1000N small many-core processors, and two hardware accelerators - an ASIC TPU-like fixed-structure systolic array acce
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::2ca297a95eccbb8dac45df1f58505b66
http://hdl.handle.net/2117/359103
http://hdl.handle.net/2117/359103