Zobrazeno 1 - 10
of 78
pro vyhledávání: '"Mason Chern"'
Publikováno v:
2022 IEEE International Test Conference (ITC).
Publikováno v:
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 39:3044-3055
Diagnosis of intermittent scan chain failures still remains a hard problem. In this article, we demonstrate that the use of artificial neural networks (ANNs) can lead to significantly higher accuracy. The key of this method is a multistage process in
Autor:
Ying-Yen Chen, Chun-Teng Chen, Shu-Yi Kao, Mango C.-T. Chao, Jih-Nung Lee, Kai-Chiang Wu, Chia-Heng Yen, Mason Chern, Ting-Rui Wang, Cheng-Hao Yang
Publikováno v:
VTS
GDBN (good die in bad neighborhood) methodology has been regarded as an effective technique for reducing DPPM (defect parts per million), by identifying and rejecting suspicious dice even though they test good. Instead of examining eight immediate ne
Autor:
Cheng-Yen Wen, Kai-Chiang Wu, Chun-Teng Chen, Ying-Yen Chen, Shu-Yi Kao, Mango C.-T. Chao, Jih-Nung Lee, Chia-Heng Yen, Mason Chern, Cheng-Hao Yang, Chun-Yi Kuo
Publikováno v:
VTS
In order to reduce DPPM (defect parts per million), IDDQ testing methodology can be exploited for identifying "outliers" which are potentially defective but not detected by signoff functional and parametric tests. Conventional IDDQ testing paradigms
Autor:
Kai-Chiang Wu, Yu-Teng Nien, Mango C.-T. Chao, Ying-Yen Chen, Shu-Yi Kao, Dong-Zhen Lee, Mason Chern, Chen Po-Lin, Jih-Nung Lee
Publikováno v:
ITC
In order to reduce DPPM (defect parts per million), cell-aware (CA) methodology was proposed to cover various types of intra-cell defects. The resulting CA faults can be a 1-time-frame (1tf) or 2-time-frame (2tf) fault, and 2tf CA tests were experime
Publikováno v:
ASP-DAC
Diagnosis of intermittent scan chain failures remains a hard problem. We demonstrate that Artificial Neural Networks (ANNs) can be used to achieve significantly higher accuracy. The key is to take on domain knowledge and use a multi-stage process inc
Publikováno v:
ISVLSI
This paper proposes a resilient Time-to-Digital Converter (TDC) that lends itself to cell-based design automation. We adopt a shrinking-based architecture with a number of distinctive techniques. First of all, a specialized on-chip re-calibration sch
Autor:
Nien, Yu-Teng, Wu, Kai-Chiang, Lee, Dong-Zhen, Chen, Ying-Yen, Chen, Po-Lin, Chern, Mason, Lee, Jih-Nung, Kao, Shu-Yi, Chao, Mango Chia-Tso
Publikováno v:
IEEE Transactions on Computer-Aided Design of Integrated Circuits & Systems; Nov2022, Vol. 41 Issue 11, p5057-5070, 14p
Autor:
Chern, Mason, Lee, Shih-Wei, Huang, Shi-Yu, Huang, Yu, Veda, Gaurav, Tsai, Kun-Han, Cheng, Wu-Tung
Publikováno v:
IEEE Transactions on Computer-Aided Design of Integrated Circuits & Systems; Sep2020, Vol. 39 Issue 10, p3044-3055, 12p
Autor:
Viehland, L. A., Fahey, D. W.
Publikováno v:
Journal of Chemical Physics; Jan1983, Vol. 78 Issue 1, p435-441, 7p