Zobrazeno 1 - 10
of 83
pro vyhledávání: '"Masaya Kawano"'
Autor:
Masaya Kawano, Xiang-Yu Wang, Qin Ren, Woon-Leng Loh, B. S. S. Chandra Rao, King-Jien Chui, Tsuyoshi Kawagoe, Ichiro Homma
Publikováno v:
2022 IEEE 72nd Electronic Components and Technology Conference (ECTC).
Autor:
Yong Han, Masaya Kawano
Publikováno v:
2021 IEEE 23rd Electronics Packaging Technology Conference (EPTC).
Publikováno v:
2021 IEEE 23rd Electronics Packaging Technology Conference (EPTC).
Publikováno v:
2021 IEEE 23rd Electronics Packaging Technology Conference (EPTC).
Publikováno v:
2021 IEEE 23rd Electronics Packaging Technology Conference (EPTC).
Publikováno v:
2021 IEEE 71st Electronic Components and Technology Conference (ECTC).
The 3D stacked DRAM is an essential key module for high-performance computing systems. However, the cost increase due to 3D stacking limits its applications. The current 3D stacking technology requires front-side and backside microbumps, temporary bo
Autor:
Wiswell Nicholas, Prayudi Lianto, Masaya Kawano, Xiangyu Wang, Vivek Chidambaram, Gilbert See
Publikováno v:
2021 IEEE 71st Electronic Components and Technology Conference (ECTC).
Wide range of choices are available for dielectric materials selection for hybrid bonding, which include: thermal oxide, PECVD TEOS SiO 2 , SiN, SiCN and commercial polymer dielectrics. Among the polymer dielectrics, two types: high-temperature curab
Autor:
Masaya Kawano
Publikováno v:
2021 5th IEEE Electron Devices Technology & Manufacturing Conference (EDTM).
This paper describes various packaging technologies and their trends for next generation heterogeneous integration. The new technologies fill the interconnect gap between chip and package to meet industry requirement of high density heterogeneous int
Publikováno v:
2020 IEEE 22nd Electronics Packaging Technology Conference (EPTC).
Three-dimensional (3D) integration via wafer stacking can provide another option for the Moore's law when the channel length of a transistor is coming to a limit of atomic scale physical dimension. There are many approaches to realize vertical interc
Publikováno v:
2020 IEEE 22nd Electronics Packaging Technology Conference (EPTC).
This paper describes the demonstration of a 4-layer wafer stack using a combination of face-to-face and back-to-back, wafer-to-wafer hybrid bonding process. Details of process flow, process characterization and challenges in multi-layer wafer stackin