Výsledky vyhledávání - "Masami Ikota"

e-beam metrology of thin resist for high NA EUVL

Autor: Gian Francesco Lorusso, Danilo De Simone, Mohamed Zidan, Joren Severi, Alain Moussa, Bappaditya Dey, Sandip Halder, Alex Goldenshtein, Kevin Houchens, Gaetano Santoro, Daniel Fischer, Angelika Muellender, Chris Mack, Tsuyoshi Kondo, Tomoyasu Shohjoh, Masami Ikota, Anne-Laure Charley, Stefan De Gendt, Philippe Leray

Publikováno v: Japanese Journal of Applied Physics. 62:SG0808

One of the many constraints of high numerical aperture extreme ultraviolet lithography is related to resist thickness. A critical consequence of moving from the current 0.33 to 0.55 NA (high NA) is depth of focus reduction. The question we seek to an

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::2ccdf54108f8c454e658d681a4ef2a0c
https://doi.org/10.35848/1347-4065/acc3a4

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Immediate observation of embedded structure after top-down delayering by using 'Dig and See' technology for GFIS-SIM based accurate overlay metrology (Conference Presentation)

Autor: Shinichi Matsubara, Masami Ikota, Hiroyasu Shichi, Tomihiro Hashizume

Publikováno v: Metrology, Inspection, and Process Control for Microlithography XXXIV.

When manufacturing a semiconductor device having a three-dimensional structure, grasping the positional relationship between the upper and lower structures is important. Our “Dig & See” technology using GFIS-SIM enables such a device to be proces

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::1aced57a842841e0d2ae9546f9975436
https://doi.org/10.1117/12.2551673

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EB metrology of Ge channel gate-all-around FET: buckling evaluation and EB damage assessment

Autor: Naoto Horiguchi, Liesbeth Witters, Kazuhisa Hasumi, Gian Lorusso, Masami Ikota, Takeyoshi Ohashi

Publikováno v: Metrology, Inspection, and Process Control for Microlithography XXXIV.

Electron beam (EB) metrology of Ge channel gate-all-around (GAA) FET (field effect transistor) was investigated. Ge-GAA FET is one of the promising candidates for high performance pMOS device of future node. Ge is superior to Si in hole mobility whic

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::25f4177c8f5951f078e2d47dd6a4e250
https://doi.org/10.1117/12.2552193

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Linewidth and roughness measurement of SAOP by using FIB and Planer-TEM as reference metrology

Autor: Gian Lorusso, Kiyoshi Takamasu, Hiroki Kawada, Masami Ikota, Frederic Lazzarino, Satoru Takahashi, Stefan Decoster

Publikováno v: Metrology, Inspection, and Process Control for Microlithography XXXIII.

In the next generation SAOP (Self-aligned Octuplet patterning) process, the line width and LWR (Line Width Roughness) measurement of lines with sub-10 nm is required. We have already proposed a novel method of line width and LWR measurement with sub-

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::fe70993cfedf55c4126fb7eaa3638f14
https://doi.org/10.1117/12.2515989

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Visualization of 3D structure of semiconductor devices by 'Dig and See' using GFIS-SIM

Autor: Sayaka Tanimoto, Shinichi Matsubara, Masami Ikota, Tomihiro Hashizume, Hiroyasu Shichi

Publikováno v: Metrology, Inspection, and Process Control for Microlithography XXXIII.

In recent years, miniaturization and multilayering have been key technologies in order to improve performance and integration of semiconductor devices. For a fine dimension control of semiconductor devices, the critical-dimension scanning electron mi

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::c4b0997d78cbbf77d177369fbe461cea
https://doi.org/10.1117/12.2514934

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Need for LWR metrology standardization: The imec roughness protocol

Autor: Anne-Laure Charley, Frieda Van Roey, Toru Ishimoto, Chami Perera, Alain Moussa, Shunsuke Koshihara, Vito Rutigliani, Takumichi Sutani, Masami Ikota, Patrick P. Naulleau, Vassilios Constantoudis, Gian Lorusso, Chris A. Mack

Publikováno v: Lorusso, GF; Sutani, T; Rutigliani, V; Van Roey, F; Moussa, A; Charley, AL; et al.(2018). Need for LWR metrology standardization: The imec roughness protocol. Journal of Micro/ Nanolithography, MEMS, and MOEMS, 17(4). doi: 10.1117/1.JMM.17.4.041009. Lawrence Berkeley National Laboratory: Retrieved from: http://www.escholarship.org/uc/item/1hz5s0w7

© 2018 Society of Photo-Optical Instrumentation Engineers (SPIE). As semiconductor technology keeps moving forward, undeterred by the many challenges ahead, one specific deliverable is capturing the attention of many experts in the field: line width

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_dedup___::02d225ced8adc2830c49210a7aea46e4
http://www.escholarship.org/uc/item/1hz5s0w7

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The need for LWR metrology standardization: the imec roughness protocol

Autor: Shunsuke Koshihara, Vito Rutigliani, Masami Ikota, Patrick P. Naulleau, Alain Moussa, Toru Ishimoto, Gian Lorusso, Frieda Van Roey, Takumichi Sutani, Anne-Laure Charley, Chris A. Mack, Vassilios Constantoudis

Publikováno v: Metrology, Inspection, and Process Control for Microlithography XXXII.

As semiconductor technology keeps moving forward, undeterred by the many challenges ahead, one specific deliverable is capturing the attention of many experts in the field: Line Width Roughness (LWR) specifications are expected to be less than 2nm in

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::424700185ae34d82f52f8b5e7b750b8d
https://doi.org/10.1117/12.2294617

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Line-width roughness of advanced semiconductor features by using FIB and planar-TEM as reference metrology

Autor: Masami Ikota, Hiroki Kawada, Kiyoshi Takamasu, Satoru Takahashi

Publikováno v: Metrology, Inspection, and Process Control for Microlithography XXXII.

LER (Line Edge Roughness) and LWR (Line Width Roughness) of the semiconductor device are an important evaluation scale of the performance of the device. Conventionally, LER and LWR is evaluated from CD-SEM (Critical Dimension Scanning Electron Micros

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::72fc41c878484311b6b4340f07463881
https://doi.org/10.1117/12.2296463

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Impact of annealing temperature on DSA process: toward faster assembly kinetics (Conference Presentation)

Autor: Paulina Rincon Delgadillo, Munirathna Padmanaban, Masami Ikota, Toru Ishimoto, Takumichi Sutani, Shunsuke Koshihara, Durairaj Baskaran, Jin Li, Yi Cao, Hyo Seon Suh, Akhil Nair, Victor Monreal, Jan Doise, Paul F. Nealey, Gian Lorusso, Takeshi Kato

Publikováno v: Advances in Patterning Materials and Processes XXXV.

Directed self-assembly (DSA) of block copolymer (BCP) thin films has been extensively researched as an alternative lithographic technology to enhance the resolution beyond the limitation of current lithography techniques.[1] One of the most critical

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::59869dbce36c50a4d02647c09e2057ec
https://doi.org/10.1117/12.2299496

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