Zobrazeno 1 - 10
of 135
pro vyhledávání: '"Masaki Hashizume"'
Autor:
Masaki Hashizume, Hiroyuki Yotsuyanagi
Publikováno v:
Journal of The Japan Institute of Electronics Packaging. 24:663-667
Autor:
Masaki Hashizume
Publikováno v:
Journal of The Japan Institute of Electronics Packaging. 24:484-487
Autor:
Masao Ohmatsu, Fumiya Sako, Yuki Ikiri, Hiroyuku Yotsuyanagi, Shyue-Kung Lu, Masaki Hashizume
Publikováno v:
2022 IEEE CPMT Symposium Japan (ICSJ).
Publikováno v:
2022 IEEE 31st Asian Test Symposium (ATS).
Autor:
Masao Ohmatsu, Yuto Ohtera, Yuki Ikiri, Hiroyuki Yotsuyanagi, Shyue-Kung Lu, Masaki Hashizume
Publikováno v:
2022 IEEE 31st Asian Test Symposium (ATS).
Autor:
Hiroyuki Yotsuyanagi, Yutaka Uematsu, Fumiya Sako, Yasuhiro Ikeda, Masaki Hashizume, Yuki Ikiri, Toru Yazaki, Shyue-Kung Lu
Publikováno v:
IEEE Transactions on Components, Packaging and Manufacturing Technology. 11:931-943
In this article, we propose two kinds of electrical interconnect test methods for production tests and field ones of assembled circuit boards, which are performed prior to and after shipping to market, respectively. For these tests, we also propose a
Autor:
Chi-Tien Sun, Chun-Lung Hsu, Hiroyuki Yotsuyanagi, Masaki Hashizume, Shu-Chi Yu, Shyue-Kung Lu
Publikováno v:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 28:634-645
By analyzing the fault behaviors of conventional flash memory fault models, two new concise fault types are proposed: the 1-safe fault and the 0-safe fault. For a 1(0)-safe fault, if logic 1(0) is programmed into the faulty cell, the effect of the fa
Publikováno v:
2021 International Conference on Electronics Packaging (ICEP).
It is discussed in this paper what resistance increase can be detected by an electrical interconnect test method that occurs after shipping to market at interconnects between ICs and printed circuit boards. The test method is based on a quiescent cur
Publikováno v:
Journal of Electronic Testing. 34:559-570
Novel fault leveling techniques based on address remapping (AR) are proposed in this paper. We can change the logical-to-physical address mapping of the page buffer such that faulty cells within a flash page can be evenly distributed into different c
Publikováno v:
IEICE Transactions on Information and Systems. :2053-2063