Zobrazeno 1 - 6
of 6
pro vyhledávání: '"Masakazu Ehama"'
Autor:
Siddhesh Darne, Teruo Takagiwa, Junya Matsuno, Yuki Shimizu, Naoya Tokiwa, Kei Shiraishi, Tetsuaki Utsumi, Hiroyuki Mizukoshi, Koji Hosono, Masatsugu Kojima, Junji Musha, Takuyo Kodama, Osamu Kobayashi, Masahiro Kano, Takeshi Hioka, Naoki Ookuma, Yuki Kuniyoshi, Takahiro Sugimoto, Ryoichi Tachibana, Hiroshi Sugawara, Hiroki Date, Kazuhide Yoneya, Srinivas Rajendra, Akira Arimizu, Yoshito Katano, Mitsuhiro Abe, Keiji Tsunoda, Masakazu Ehama, Toshifumi Hashimoto, Tianyu Tang, Tomofumi Fujimura, Ryo Fukuda, Jason Li, Hiroshi Maejima, Shintaro Hayashi, Akio Sugahara, Kei Akiyama, Koji Kato, Toru Miwa, Kensuke Yamamoto, Masahiro Yoshihara, Katsuaki Sakurai, Itaru Yamaguchi, Tsutomu Higuchi, Mizuki Kaneko, Jumpei Sato, Kazumasa Yamamoto, Yasuhiro Suematsu, Mitsuyuki Watanabe, Ryuji Yamashita, Venky Ramachandra, Kosuke Yanagidaira, Jiwang Lee, Kazuko Inuzuka, Hirotoshi Mori, Takatoshi Minamoto, Tomoharu Hashiguchi, Mitsuaki Honma, Juan Lee
Publikováno v:
ISSCC
This work demonstrates a novel 1Tb 3D Flash memory chip that has an area efficiency of 10.4Gb/mm2 in a 3b/cell technology. Using a circuit under array (CUA) design technique and over 170 word-line (WL) layers, the chip achieves 33% higher bit density
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::246d299cae34d3af1b49b01f6b5bee4c
https://doi.org/10.1109/isscc42613.2021.9366003
https://doi.org/10.1109/isscc42613.2021.9366003
Autor:
Hiroshi Ueda, Keiji Matsumoto, Hiromi Watanabe, Shinichi Yoshioka, Katsuji Takakubo, Kenichi Iwata, Takahiro Irita, Seiji Mochizuki, Jun Takemura, Motoki Kimura, Eiji Yamamoto, Toshihiro Hattori, Masakazu Ehama, Tadashi Teranuma
Publikováno v:
IEEE Journal of Solid-State Circuits. 45:59-68
A full-HD (1080p30) 500 MHz mobile application processor with an H.264 HP/MPEG-2/MPEG-4 video codec is integrated on a 6.4 × 6.5 mm2 die in 65 nm low-power CMOS. With two parallel pipelines for macroblock processing and tile-based address translatio
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::9eb54ad2acdd416881d70c1b41a908fd
https://doi.org/10.1109/jssc.2009.2031797
https://doi.org/10.1109/jssc.2009.2031797
Publikováno v:
IEEE Micro. 29:18-27
A full high-definition (full HD) video codec includes a high-performance stream processing unit to support multiple standards in mobile application processors. The unit performs at 40 Mbps when operated at a 162-MHz clock rate. Implemented in 65-nm C
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::9de65664aa7f0bbbbe2d25fd8a137b9c
https://doi.org/10.1109/mm.2009.87
https://doi.org/10.1109/mm.2009.87
Autor:
Hiroshi Ueda, Motoki Kimura, Hiromi Watanabe, Kenichi Iwata, Masakazu Ehama, Hiroaki Nakata, Takuichiro Nakazawa, Seiji Mochizuki, Toru Kengaku, Koji Hosogi, Tetsuya Shibayama, Fumitaka Izuhara
Publikováno v:
IEEE Journal of Solid-State Circuits. 44:1184-1191
A video-size-scalable H.264 high-profile codec including 19 application-specific CPUs for extensibility to multiple standards has been fabricated in 65 nm CMOS. With two parallel pipelines for macroblock processing, the codec consumed 256 mW in real-
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::162caacc02a15c3b687c9819c739215d
https://doi.org/10.1109/jssc.2009.2014025
https://doi.org/10.1109/jssc.2009.2014025
Autor:
Tadashi Teranuma, Motoki Kimura, Hiromi Watanabe, Masakazu Ehama, Toshihiro Hattori, Takahiro Irita, Jun Takemura, S. Yoshioka, Seiji Mochizuki, Katsuji Takakubo, Hiroshi Ueda, Keiji Matsumoto, Kenichi Iwata, Eiji Yamamoto
Publikováno v:
ISSCC
Today's cellular phones must support full high-definition (full-HD) video in multiple video formats, such as H.264 and MPEG-2/-4, with low power consumption. Full-HD video processing requires six times the data bandwidth and is more computationally i
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::61be725445ac46c6cbf95e928403e6c5
https://doi.org/10.1109/isscc.2009.4977356
https://doi.org/10.1109/isscc.2009.4977356
Autor:
Hiroaki Nakata, Masakazu Ehama, Seiji Mochizuki, Toru Kengaku, Hiromi Watanabe, Takuichiro Nakazawa, Hiroaki Ueda, Fumitaka Izuhara, Koji Hosogi, Tetsuya Shibayama, Kenichi Iwata
Publikováno v:
2008 IEEE Symposium on VLSI Circuits.
A video-size-scalable H.264 high-profile CODEC including 19 specific CPUs for extensibility to multiple standards has been fabricated in 65 nm CMOS. With two parallel pipelines for macroblock processing, the CODEC consumed 256 mW in real-time encodin
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::93eb6b37e007e7d533f283456935ee54
https://doi.org/10.1109/vlsic.2008.4585968
https://doi.org/10.1109/vlsic.2008.4585968