Zobrazeno 1 - 9
of 9
pro vyhledávání: '"Masakatsu Ishizaki"'
Autor:
Takeshi Kumaki, M. Nakajima, Masaru Haraguchi, Masakatsu Ishizaki, T. Nishijima, E. Shimomura, Tetsushi Koide, Kazutami Arimoto, Shunsuke Kamijo, K. Murata, Yuta Imai, Y. Okuno, Takeaki Sugimura, Hans Jurgen Mattausch, Tetsushi Tanizaki, Hiroyuki Yamasaki, Hideyuki Noda, K. Yoshida, T. Kurafuji
Publikováno v:
ISSCC
This paper describes a high performance scalable massively parallel single-instruction multiple-data (SIMD) processor and power/area efficient real-time image processing. The SIMD processor combines 4-bit processing elements (PEs) with SRAM on a smal
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::2c6e9b06c3a415d0e938d6aaab6318ae
https://doi.org/10.1109/jssc.2011.2159528
https://doi.org/10.1109/jssc.2011.2159528
Publikováno v:
IEICE Transactions on Information and Systems. :1742-1754
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::aeed03315d2e8bc6356121c699613829
https://doi.org/10.1587/transinf.e94.d.1742
https://doi.org/10.1587/transinf.e94.d.1742
Autor:
Katsumi Dosaka, Takeshi Kumaki, Yasuto Kuroda, Tetsushi Koide, Kazutami Arimoto, Masakatsu Ishizaki, Kazunori Saito, Hans Jurgen Mattausch, Hideyuki Noda, T. Gyohten
Publikováno v:
IEICE Transactions on Electronics. :1409-1418
This paper presents an integration architecture of content addressable memory (CAM) and a massive-parallel memory-embedded SIMD matrix for constructing a versatile multimedia processor. The massive-parallel memory-embedded SIMD matrix has 2,048 2-bit
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::e0518effe5af93a71c38d735dcbc0879
https://doi.org/10.1093/ietele/e91-c.9.1409
https://doi.org/10.1093/ietele/e91-c.9.1409
Autor:
Yasuto Kuroda, Kazutami Arimoto, Hans Jurgen Mattausch, Kazunori Saito, Tetsushi Koide, Hideyuki Noda, Takeshi Kumaki, Katsumi Dosaka, Masakatsu Ishizaki
Publikováno v:
IEICE Transactions on Information and Systems. :1312-1315
This paper reports an efficient Discrete Cosine Transform (DCT) processing method for images using a massive-parallel memory-embedded SIMD matrix processor. The matrix-processing engine has 2,048 2-bit processing elements, which are connected by a fl
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::82e3358ec7030cf0c8b7d3f2d111397b
https://doi.org/10.1093/ietisy/e90-d.8.1312
https://doi.org/10.1093/ietisy/e90-d.8.1312
Publikováno v:
IEICE Transactions on Information and Systems. :346-354
This paper presents a scalable FPGA/ASIC implementation architecture for high-speed parallel table-lookup-coding using multi-ported content addressable memory, aiming at facilitating effective table-lookup-coding solutions. The multi-ported CAM adopt
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::10f7b11cc113fae0062fa45e302241be
https://doi.org/10.1093/ietisy/e90-1.1.346
https://doi.org/10.1093/ietisy/e90-1.1.346
Autor:
Yasuto Kuroda, Hans Jurgen Mattausch, Takeshi Kumaki, Masakatsu Ishizaki, Tetsushi Koide, Hideyuki Noda, Kazutami Arimoto, Katsumi Dosaka, Kazunori Saito
Publikováno v:
IEICE Transactions on Information and Systems. :334-345
This paper presents a novel optimized real-time Huffman encoder using a pipelined data path based on CAM technology and a parallel code-word-table optimizer. The exploitation of CAM technology enables fast parallel search of the code word table. At t
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::944aef03060e9080bfa71bc6dffc3848
https://doi.org/10.1093/ietisy/e90-1.1.334
https://doi.org/10.1093/ietisy/e90-1.1.334
Autor:
Hans Juergen Mattausch, Tetsushi Koide, Hideyuki Noda, T. Gyohten, Yutaka Kono, Katsumi Dosaka, Kazutami Arimoto, Masaharu Tagami, Takeshi Kumaki, Kazunori Saito, Yasuto Kuroda, Masakatsu Ishizaki
Publikováno v:
2007 50th Midwest Symposium on Circuits and Systems.
A super parallel SIMD processor has been proposed as a novel SIMD multimedia processor, which is better way for processing several types multimedia data. This processor supports 2,048-way bit-serial and word-parallel operation. Moreover, 2,048 Proces
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::4110819d7a8aad97adbad97f7553dad0
https://doi.org/10.1109/mwscas.2007.4488697
https://doi.org/10.1109/mwscas.2007.4488697
Publikováno v:
APCCAS
This paper presents a parallel coding architecture using a flexible multi-ported content addressable memory (CAM). A previously reported flexible multi-port content addressable memory (FMCAM) technology (Kumaki et al., 2004) is improved by additional
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::d654c170c4d5c080a8f2cd0480f41519
https://doi.org/10.1109/apccas.2006.342201
https://doi.org/10.1109/apccas.2006.342201
Autor:
Yasuto Kuroda, Takayuki Gyoten, Takeshi Kumaki, Tetsushi Koide, Kazunori Saito, Katsumi Dosaka, Kazutami Arimoto, Hans Jurgen Mattausch, Masakatsu Ishizaki, Hideyuki Noda, Y. Kouno
Publikováno v:
TENCON 2006 - 2006 IEEE Region 10 Conference.
This paper presents a method for achieving high speed and high compression ratio of Huffman encoding by updating and optimizing the code word table. A shadow code word table is continuously reconstructed according to the frequency distribution of the
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::2b8cb1f1048e963101f47508e1d005a8
https://doi.org/10.1109/tencon.2006.344025
https://doi.org/10.1109/tencon.2006.344025