Zobrazeno 1 - 10
of 12
pro vyhledávání: '"Mary P. Kusko"'
Publikováno v:
IBM Journal of Research and Development. 43:899-914
This paper describes the strategies and techniques used to diagnose failures in the IBM 600-MHz S/390® G5 (Generation 5) CMOS microprocessor and the associated cache chips. The complexity, density, cycle time, and technology issues related to the ha
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::1d2fdf38a75de7db1fac3c5081056f6c
https://doi.org/10.1147/rd.435.0899
https://doi.org/10.1147/rd.435.0899
Autor:
Mary P. Kusko, T.G. Foote, Bryan J. Robbins, William V. Huott, Timothy J. Koprowski, D.E. Hoffman
Publikováno v:
IEEE Design & Test of Computers. 15:83-89
The design-for-test framework of the 500-MHz CMOS central processor uses specific tests to ensure the highest reliability of components within a system. Some of the same test patterns are applied in chip manufacturing and system-level tests.
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::0d22e225dc7da4201e6d70f14b23b05d
https://doi.org/10.1109/54.706038
https://doi.org/10.1109/54.706038
Autor:
Timothy G. McNamara, T.J. Snethen, Timothy J. Koprowski, William V. Huott, S. V. Pateras, Dale Eugene Hoffman, Mary P. Kusko, Bryan J. Robbins
Publikováno v:
IBM Journal of Research and Development. 41:611-627
This paper describes the overall test methodology used in implementing the S/390® microprocessor and the associated L2 cache array in shared multiprocessor designs, the design-for-test implementations, and the test software used in creating the test
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::e6892d288e9429b096c3d9517f24ff0c
https://doi.org/10.1147/rd.414.0611
https://doi.org/10.1147/rd.414.0611
Autor:
Mary P. Kusko, Edward Michael Seymour, B. Walsh, Orazio P. Forlenza, Donato O. Forlenza, Timothy D. Taylor, James M. Crafts, Dennis R. Conti, William V. Huott, David C. Bogdan
Publikováno v:
ITC
The IBM Power 7™ 4 GHz, eight core microprocessor introduced several new challenges for the Power 7 test team: new pervasive test architecture, 8 asynchronous processor cores, DRAM integrated on the same die as processor and enhanced thermal test r
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::dbf65da51ebe36eee4060cf2febb9171
https://doi.org/10.1109/test.2010.5699204
https://doi.org/10.1109/test.2010.5699204
Publikováno v:
ITC
This paper presents a new approach to improve random test coverage during physical synthesis for high performance design. This new approach performs test point insertion (TPI) to improve testability of random resistant nets. Conventional test point i
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::c48333ebfb2c23d497022f6b56aff759
https://doi.org/10.1109/test.2009.5355747
https://doi.org/10.1109/test.2009.5355747
Autor:
Daniel R. Knebel, Moyra K. McManus, J. Lee, Peilin Song, Mary P. Kusko, Franco Motika, Richard F. Rizzolo
Publikováno v:
ITC
This paper describes strategies and techniques used to diagnose failures in the IBM 600 MHz G5 (Generation 5) CMOS microprocessor and associated cache chips. Time-to-market pressure demands quick diagnostic turnaround time while the complexity, densi
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::d69731b80f84f62f2841376ce07d3212
https://doi.org/10.1109/test.1999.805841
https://doi.org/10.1109/test.1999.805841
Publikováno v:
ITC
This paper describes the test tool methodology used for the IBM S/390 microprocessor. An efficient, effective, and automated process providing correct-by-construction test pattern generation, an effective test pattern set, and diagnostics were requir
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::f748827698b543611d0eec167cd379da
https://doi.org/10.1109/test.1998.743216
https://doi.org/10.1109/test.1998.743216
Autor:
T.G. Foote, William V. Huott, Bryan J. Robbins, Mary P. Kusko, Timothy J. Koprowski, D.E. Hoffman
Publikováno v:
ITC
This paper describes the design-for-test framework of the 400 MHz CMOS central processor (CP) used in the fourth generation (G4) of the IBM S/390(R) line of servers. It will describe details of modeling logic to achieve correct and effective tests as
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::d5082babc289769754bdf011f92aa97f
https://doi.org/10.1109/test.1997.639601
https://doi.org/10.1109/test.1997.639601
Autor:
C. Hirko, R. Yaari, Ulrich Baur, D. W. Wittig, J. A. Kyle, Orazio P. Forlenza, Donato O. Forlenza, Mary P. Kusko, Bryan J. Robbins, Gerard M. Salem, Franco Motika, S. Michnowski, T.G. Foote, Ronald J. Frishmuth
Publikováno v:
IBM Journal of Research and Development. 53:5:1-5:11
For the first time in the history of the IBM System z™ family of mainframes, System z10™ processor chips are tested by both structural and functional means. This complementary strategy starts at wafer test and is consistent through system test. I
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::44b3f6146dbb85fd9c1f8c9288b41828
https://doi.org/10.1147/jrd.2009.5388583
https://doi.org/10.1147/jrd.2009.5388583
Conference
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