Zobrazeno 1 - 10
of 16
pro vyhledávání: '"Martin Saint-Laurent"'
Autor:
Martin Saint-Laurent, Alain.
Thèse--Méd.--Paris 11, 1972. N°: N° 11.
Bibliogr.
Bibliogr.
Externí odkaz:
http://catalogue.bnf.fr/ark:/12148/cb35898233r
Autor:
Ken Lin, Dwight Galbi, Yuhe Wang, Kartik Ayyar, Tom Wernimont, Xufeng Chen, Marzio Pedrali-Noy, Paul Bassett, Dan Bui, Maen Alradaideh, Willie Anderson, Allan Lester, Baker Mohammad, Martin Saint-Laurent
Publikováno v:
ISSCC
This paper describes the implementation of a Qualcomm Hexagon digital signal processor (DSP) in a 28 nm high-κ metal gate technology. The DSP is a multi-threaded very-long- instruction-word (VLIW) machine optimized for low leakage and energy efficie
Publikováno v:
ICCD
We describe a methodology to model the low power and voltage behavior of multi-voltage custom memories in processors. These models facilitate early power-aware verification by abstracting the transistor-level representation of the memory to its power
Autor:
Martin Saint-Laurent
Transistor technology scaling has deviated from the ideal constant-field scaling discussed by Dennard et al . in [1]. In particular, since the 90-nm technology node, the supply voltage has been going down slowly, if at all. This non-ideal scaling has
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::444b6271fefc55cbcb6f174bddb62ee9
https://doi.org/10.1017/cbo9781316156148.008
https://doi.org/10.1017/cbo9781316156148.008
Autor:
Martin Saint-Laurent, Paul Bassett, Ken Lin, Yuhe Wang, Son Le, Xufeng Chen, Maen Alradaideh, Tom Wernimont, Kartik Ayyar, Dan Bui, Dwight Galbi, Allan Lester, Willie Anderson
Publikováno v:
2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC).
Autor:
Paul Bassett, Martin Saint-Laurent
Publikováno v:
ICICDT
Power is often cited as a key design metric for IC designs. However, for many integrated solutions a better measure of design quality is the overall energy efficiency of the design as low power does not always imply high energy efficiency. Many desig
Autor:
Martin Saint-Laurent, Animesh Datta
Publikováno v:
ISLPED
This paper discusses a novel clock gating cell (CGC) optimized for low-power and low-voltage operation. First, the limitations of the conventional CGC topology are analyzed and several improvements are proposed. Next, the new CGC topology is introduc
Publikováno v:
Applied optics. 39(5)
A field-programmable logic device (FPLD) with optical I/O is described. FPLD's with optical I/O can have their functionality specified in the field by means of downloading a control-bit stream and can be used in a wide range of applications, such as
Publikováno v:
ISQED
A novel circuit approach to increase SRAM static noise margin (SNM) and enable lower operating voltage is described. Increasing process variability [1] [2] for new technologies coupled with increased reliability effects like negative bias temperature
Publikováno v:
ISLPED
This paper discusses the technology limits placed on the clock switching energy in sequential elements. It proposes a novel pulsed latch that uses a single clocked transistor and consumes close to ten times less clock power than a conventional latch