Zobrazeno 1 - 10
of 20
pro vyhledávání: '"Martin Knaipp"'
Autor:
Martin Knaipp, Giorgio Badino, Enrico Brinciotti, Juergen Smoliner, Georg Gramse, Ferry Kienberger
Publikováno v:
IEEE Transactions on Nanotechnology. 16:245-252
We quantitatively image the doping concentration and the capacitance of a high-voltage lateral metal-oxide-semiconductor transistor device with a channel length of 0.5 μm at 20-GHz frequency using scanning microwave microscopy (SMM). The transistor
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::80c85bdb3075737eff6d36e630062d9e
https://doi.org/10.1109/tnano.2017.2657888
https://doi.org/10.1109/tnano.2017.2657888
Autor:
Y. Yamamoto, Martin Knaipp, D. Bolze, Ewald Wachmann, M. Sekowski, Peter Pichler, Martin Schrems, S. Koffel, Alexander Burenkov, Damiano Giubertoni, Massimo Bersani
Publikováno v:
physica status solidi c. 11:12-15
One of the main issues for the simulation of MOS transistors is the correct prediction of threshold voltages that depend on the active doping profiles in the channel under the gate oxide. Simulating a power MOS process we encountered a situation in w
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::670b9703da5dc299149c90ad67a6db07
https://doi.org/10.1002/pssc.201300152
https://doi.org/10.1002/pssc.201300152
Publikováno v:
ATZelektronik worldwide. 8:40-44
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::287f475c105e1091b56bee30f56a04d3
https://doi.org/10.1365/s38314-013-0211-9
https://doi.org/10.1365/s38314-013-0211-9
Publikováno v:
ATZelektronik. 8:458-464
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::030154b668941472591ae2c544ca054d
https://doi.org/10.1365/s35658-013-0366-4
https://doi.org/10.1365/s35658-013-0366-4
Autor:
Heimo Gensinger, Friedrich Peter Leisenberger, Martin Schrems, E. Seebacher, Hubert Enichlmair, Rainer Minixhofer, Ewald Wachmann, Gregor Schatzberger, Martin Knaipp, Verena Vescoli
Publikováno v:
e & i Elektrotechnik und Informationstechnik. 125:109-117
Integration of low voltage analog and logic circuits as well as high-voltage (HV) devices for operation at greater than 5 V enables Smart Power ICs used in almost any system that contains electronics. HVCMOS (High-Voltage CMOS) technologies offer muc
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::0a4636b6b7b266dade7db3f906f5a0ac
https://doi.org/10.1007/s00502-008-0519-y
https://doi.org/10.1007/s00502-008-0519-y
Publikováno v:
Microelectronics Journal. 37:243-248
This work describes the evolution of a CMOS based lateral high voltage (HV) technology concept, where the HV part is integrated in a low voltage (LV) CMOS technology. The starting point is an existing substrate related state of the art 0.35 μm LV CM
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::b4738839a21a9a844f8ab708df9eee6a
https://doi.org/10.1016/j.mejo.2005.09.014
https://doi.org/10.1016/j.mejo.2005.09.014
Publikováno v:
The European Physical Journal Applied Physics. 21:103-106
Optimizing process- and layout-design in the development of modern electronic devices is key to achieve required characteristics. Coming along with the growing complexity of device structures, associated effects must be considered in an even more com
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::e0b647128c5ff8debedb99a6adb9e17a
https://doi.org/10.1051/epjap:2002121
https://doi.org/10.1051/epjap:2002121
Publikováno v:
Solid-State Electronics. 44:1135-1143
The breakdown of an overvoltage protection structure is analyzed in the temperature range from 298 to 523 K. The avalanche generation rates are modeled as a function of the carrier and lattice temperature. The generation rates are proportional to the
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::14b694eeb1ea05f135dc349d1b79b752
https://doi.org/10.1016/s0038-1101(00)00046-0
https://doi.org/10.1016/s0038-1101(00)00046-0
Autor:
Martin Knaipp, Hubert Enichlmair, Yun Shi, Jong Mun Park, Natalie B. Feilchenfeld, Rainer Minixhofer
Publikováno v:
2012 24th International Symposium on Power Semiconductor Devices and ICs.
This work reports the hot-carrier (HC) behavior and specific on-resistance (R on,sp ) optimization of 20∼60 V p-channel LDMOS transistors implemented in a 180 nm HV-CMOS technology. By precise control the implant dose and energy of a p-drift region
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::5db23cf880b59eaf2892dd433e44897d
https://doi.org/10.1109/ispsd.2012.6229055
https://doi.org/10.1109/ispsd.2012.6229055
Publikováno v:
2011 IEEE 23rd International Symposium on Power Semiconductor Devices and ICs.
In this paper, we discuss the scalable NLDMOS design in a 0.18μm HV-CMOS technology. The design impacts in quasi-saturation are compared between the 25V and 50V NLDMOS to demonstrate the implications in output and f T characteristics. The STI depth
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::a254f37e54661a5fc5a2f6272adadfeb
https://doi.org/10.1109/ispsd.2011.5890829
https://doi.org/10.1109/ispsd.2011.5890829