Zobrazeno 1 - 7
of 7
pro vyhledávání: '"Martin Kinkade"'
Publikováno v:
ISCAS
As CMOS technology scales with complex lithography, metal resistance increases. Specifically, at high-temperatures IR drop limits the performance and impacts the yield of CMOS circuits. For SRAM, bitline resistance limits the writeability of bitcells
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::0a82a50174a0b077be5a5dfbbbec0cc3
https://doi.org/10.1109/iscas51556.2021.9401420
https://doi.org/10.1109/iscas51556.2021.9401420
Self-timed Power-on Reset Circuit for Pseudo Dual/Two Port SRAM Used in Low-Voltage IoT Applications
Publikováno v:
VLSI-SoC: Opportunities and Challenges Beyond the Internet of Things ISBN: 9783030156626
VLSI-SoC (Selected Papers)
VLSI-SoC (Selected Papers)
The purpose of the Power-on Reset (POR) circuit is to reset the latches and flip-flops in an SOC to a known state when the supply is ramping up. During power-up, supply is not stable, and the ramp-up time can vary depending on the applications. A com
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::ea04e3ccce9fd184336489e0013a8066
https://doi.org/10.1007/978-3-030-15663-3_5
https://doi.org/10.1007/978-3-030-15663-3_5
Autor:
Satinderjit Singh, Fakhruddin ali Bohra, Sagar Dwivedi, Martin Kinkade, Vivek Nautiyal, Jitendra Dasani, Nishant Nukala, Gaurav Singla
Publikováno v:
ISQED
In this paper, a row-redundancy circuit using latches is designed for 7nm FinFET ultra high density SRAM operating at 1.75 GHz. Input and faulty addresses are compared in parallel to the memory read access operation thus avoiding a major impact on ac
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::368e7c33b95fa104f310c78efe7b6bc4
https://doi.org/10.1109/isqed.2018.8357300
https://doi.org/10.1109/isqed.2018.8357300
Publikováno v:
VLSI-SoC
The purpose of the Power-on Reset (POR) circuit is to reset the latches and flip-flops in an SOC to a known state when the supply is ramping up. During power-up, supply is not stable, and the ramp-up time can vary depending on the applications. A com
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::e19ab6f40ecf53ef82aa66d4e5cdbbec
https://doi.org/10.1109/vlsi-soc.2017.8203474
https://doi.org/10.1109/vlsi-soc.2017.8203474
Autor:
Abhishek Baradia, Andy Wangkun Chen, Mudit Bhargava, Bikas Maiti, Jacek Wiatrowski, Vincent Schuppe, Sriram Thyagarajan, Gus Yeung, Yew Keong Chong, Hsin-Yu Chen, Gerald Gouya, Sanjay Mangal, Martin Kinkade
Publikováno v:
VLSIC
Measured results of V MIN from 20nm SRAM arrays with read and write assist techniques are presented for multiple flavors of bitcell. A novel assist technique is presented, that provides both read and write assist by controlling only the voltage of wo
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::e6687cecbc4db99b6d22e0a792f8944c
https://doi.org/10.1109/vlsic.2014.6858412
https://doi.org/10.1109/vlsic.2014.6858412
Autor:
Jian Shen, Chen-chau Chu, Tony Hurson, Guanghui Hu, Martin Kinkade, Dave Baker, Jacob A. Abraham, Gregorio Gervasio
Publikováno v:
DAC
The advanced VLIW architecture of the Equator MAP1000 processor has many features that present significant verification challenges. We describe a functional verification methodology to address this complexity. In particular, we present an efficient m
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::f6571084669370654d94369a2b4da1e9
https://doi.org/10.1145/309847.309908
https://doi.org/10.1145/309847.309908
Conference
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