Zobrazeno 1 - 6
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pro vyhledávání: '"Mark P. McCartney"'
Autor:
Mark R. Theobald, Mark C. Milford, Mark K.J. Hargreaves, Mark L.J. Sheppard, Mark E. Nemitz, Mark Y.S. Tang, Mark V. R. Phillips, Mark R. Sneath, Mark L. McCartney, Mark F. J. Harvey, Mark I. D. Leith, Mark J. N. Cape, Mark D. Fowler, Mark M. A. Sutton
Publikováno v:
The Scientific World Journal, Vol 1, Pp 791-801 (2001)
There has been increasing pressure on farmers in Europe to reduce the emissions of ammonia from their land. Due to the current financial climate in which farmers have to operate, it is important to identify ammonia control measures that can be adopte
Externí odkaz:
https://doaj.org/article/5e3e8bab398f481ea982631948c83a1e
Autor:
Andy Wangkun Chen, Mudit Bhargava, Tan Peixuan, Yulin Shi, Mark P. McCartney, Yew Keong Chong, Cagla Cakir, Sriram Thyagarajan
Publikováno v:
VLSI Circuits
We present a high-performance 6T SRAM architecture equipped with low-power features of late cancel, left-right enable, input-gating, and power-gating. Measurements show that these SRAMs can support CPUs running at 4GHz while offering dynamic power sa
Publikováno v:
FCCM
NAND flash memory has been widely used for data storage due to its high density, high throughput, low cost, and low power. However, as flash memory manufacturers scale to smaller process technologies and store more bits per cell, the reliability and
Publikováno v:
FPGA
NAND Flash memory has been widely used for data storage due to its high density, high throughput, low cost, and low power. However, as the storage cells become smaller and with more bits programmed per cell, they are expected to suffer from reduced r
Publikováno v:
CICC
Device variability in modern processes has become a major concern in SRAM design, degrading performance, yield, power, and reliability. While low-swing bitlines can reduce power consumption and increase performance, offset in the sense amplifiers due
Publikováno v:
CICC
A configurable replica bitline (cRBL) technique for controlling sense-amplifier enable (SAE) timing for small-swing bitline SRAMs is described. Post-silicon selection of a subset of replica bitline driver cells from a statistically designed pool of c