Zobrazeno 1 - 7
of 7
pro vyhledávání: '"Mario Caresosa"'
Autor:
Namik Kocaman, Ullas Singh, Bharath Raghavan, Arvindh Lyer, Kumar Thasari, Saurabh Surana, Jun Won Jung, Jaehun Jeong, Heng Zhang, Anand Vasani, Yonghyun Shim, Zhi Huang, Adesh Garg, Hsiang-bin Lee, Bo Wu, Feifei Liu, Ray Wang, Matthew Loh, Alex Wang, Mario Caresosa, Bo Zhang, Afshin Momtaz
Publikováno v:
2022 IEEE International Solid- State Circuits Conference (ISSCC).
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::1f492f0be2b9e8c05f9d57cd98ce3864
https://doi.org/10.1109/isscc42614.2022.9731688
https://doi.org/10.1109/isscc42614.2022.9731688
Publikováno v:
IEEE Journal of Solid-State Circuits. 42:872-880
A 10 Gb/s receiver, containing an adaptive equalizer, a clock and data recovery, and a de-multiplexer, is implemented in 0.13-mum CMOS. The chip is intended for long-haul optical fiber links where chromatic and polarization mode dispersions are reach
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::d31874a2295850f3bf833e43d95b7f53
https://doi.org/10.1109/jssc.2007.892166
https://doi.org/10.1109/jssc.2007.892166
Autor:
Armond Hairapetian, Keh-Chee Jen, Mario Caresosa, Yijun Cai, Ichiro Fujimori, Afshin Momtaz, Jun Cao, Kambiz Vakilian, Michael M. Green, D. Chung, Wee-Guan Tan
Publikováno v:
IEEE Journal of Solid-State Circuits. 36:1964-1973
This paper presents the first fully integrated, SONET OC-48 (2.488/2.666 Gb/s) transceiver using a standard CMOS process. Careful design methodology combined with a standard CMOS technology allows performance exceeding SONET requirements with the add
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::bd47a9e1f65427f6275839305a115b21
https://doi.org/10.1109/4.972147
https://doi.org/10.1109/4.972147
Autor:
Seong-Ho Lee, Hui Pan, Haitao Tong, Wei Zhang, Hamid Hatamkhani, Duke Tran, Magesh Valliappan, Ichiro Fujimori, Karo Khanoyan, Anthony Brewster, Mario Caresosa, Kambiz Vakilian
Publikováno v:
ISSCC
It has been well understood that the digital clock and data recovery (CDR) architecture has many system merits over the analog counterpart for multi-Gb/s transceivers [1]. However, the applications have been limited in systems where the clock is forw
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::00828fb6cf4870c4e8e01d6e8302ca4b
https://doi.org/10.1109/isscc.2011.5746389
https://doi.org/10.1109/isscc.2011.5746389
Autor:
Ichiro Fujimori, Mario Caresosa, D. Chung, Ben Tan, Kambiz Vakilian, Afshin Momtaz, Armond Hairapetian, Keh-Chee Jen, Jun Cao, Michael M. Green
Publikováno v:
2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315).
A fully integrated OC-192 multi-rate (9.95Gb/s-10.71Gb/s) receiver uses standard 0.18/spl mu/m CMOS. The circuit consists of an input amplifier, CDR, 1:16 demux and 18 LVDS drivers. The chip exceeds SONET jitter tolerance spec by >100%. Recovered 10G
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::94ad526d6cf7c01aba2968dbcd5ef04d
https://doi.org/10.1109/isscc.2002.992213
https://doi.org/10.1109/isscc.2002.992213
Autor:
Jun Cao, Kambiz Vakilian, Xin Wang, Michael M. Green, Yijun Cai, D. Chung, Afshin Momtaz, Armond Hairapetian, Keh-Chee Jen, Ichiro Fujimori, Mario Caresosa
Publikováno v:
2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315).
A fully integrated SONET OC-192 transmitter IC using a standard CMOS process consists of an input data register, FIFO, CMU, and 16:1 multiplexer to give a 10Gb/s serial output. A higher FEC rate, 10.7Gb/s, is supported. This chip, using a 0.18/spl mu
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::bda44b4d5020b043308d68d8713abb98
https://doi.org/10.1109/isscc.2002.992212
https://doi.org/10.1109/isscc.2002.992212
Autor:
K. Vakitian, Mario Caresosa, Yijun Cai, A. Hairapitian, Keh-Chee Jen, G. Gutierrez, Michael M. Green, Afshin Momtaz, D. Chung, Ichiro Fujimori, Jun Cao, B. Tan
Publikováno v:
2001 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC (Cat. No.01CH37177).
A fully-integrated transceiver in standard 0.18 /spl mu/m CMOS exceeds all SONET OC-48 requirements. The serial interfaces are 2.488 or 2.667 Gb/s CMC and the parallel ones are 622 or 666 Mb/s LVDS. The output clock rms jitter is 1 ps and total power
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::3a781a23aeea7d3a6f620d562c2db4b3
https://doi.org/10.1109/isscc.2001.912553
https://doi.org/10.1109/isscc.2001.912553