Zobrazeno 1 - 10
of 15
pro vyhledávání: '"Mariam Sadaka"'
Autor:
Thomas Signamarcheix, Thomas Lacave, Gweltaz Gaudin, Mariam Sadaka, Lea Di Cioccio, Ionut Radu, Floriane Baudin
Publikováno v:
ECS Transactions. 58:17-28
3D integration aims at providing highly integrated systems by vertically stacking and connecting various materials, technologies, and functional components together. We will review the different approaches, using direct bonding, developed to address
Publikováno v:
ICICDT
The wafer stacking technology for 3D integration requires high quality bonding interfaces with uniform bonding films. Two wafer level stacking technologies - Smart Stacking™ and Smart Cut™ - are developed to address the manufacturing challenges f
Publikováno v:
2011 IEEE International Conference on IC Design & Technology.
Smart Stacking™ is a wafer-to-wafer stacking technology of partially or fully processed wafers. This technology enables transferring very thin layers in a high volume manufacturing environment. The core technologies are surface conditioning, low te
Autor:
Michael J. Darwin, Gregory Riou, Kevin R. Winstel, Catherine Tempesta, Emily R. Kinser, Mariam Sadaka, Robert Sachs, Gweltaz Gaudin, Boris V. Kamenev, Ionut Radu, Robert Hannon, Didier Landru
Publikováno v:
3DIC
This article reports the capability and the recent development of optical profilometry for monitoring 3D integrated circuits. In particular, the capability to profile transparent film stacks, which was quite challenging, is now accessible with the Un
Autor:
Mariam Sadaka, Robert Hannon, Kevin R. Winstel, Gweltaz Gaudin, Gregory Riou, Catherine Tempesta, Emily R. Kinser, Didier Landru, Ionut Radu
Publikováno v:
3DIC
In this paper the integration challenges related to oxide-oxide bonding for wafer-to-wafer stacking technology are discussed. Furthermore, interface defectivity, wafer-to-wafer alignment and bond strength data are presented.
Autor:
Jerome Dechamp, C. Euvrard, Gregory Riou, Thomas Signamarcheix, Laurent Clavelier, L. Di Cioccio, Mariam Sadaka, P. Gueguen, Gweltaz Gaudin, Fabrice Letertre, Ionut Radu, Didier Landru, Catherine Tempesta
Publikováno v:
3DIC
This paper will focus on recent results of Cu-Cu non-thermo compression bonding for wafer-to-wafer 3D stacking. We report on bonding quality, wafer-to-wafer alignment accuracy and electrical connectivity. Specific pre-bonding surface conditioning is
Publikováno v:
2010 IEEE International Conference on Integrated Circuit Design and Technology.
3D integration is a promising and fast growing field that addresses the convergence of Moore's Law and more than Moore. 3D integration offers higher performance, higher density, higher functionality, smaller form factor, and potential cost reduction.
Publikováno v:
2010 IEEE International Conference on Integrated Circuit Design and Technology.
The microelectronic industry has arrived at a crossroads. There is the challenge of continued Moore's Law scaling and the ever-growing consumer demand for smaller, faster electronics with extended and new functionalities. 3D integration is a promisin
Autor:
M. Canonico, Mong-Song Liang, Linda B. McCormick, Stefan Zollner, Aaron Thean, Laegu Kang, R. Noble, Marius K. Orlowski, Venkat R. Kolagunta, X.-D. Wang, Jon D. Cheek, Y.C. Sun, M. Zavala, M. Ramon, Mark Kennard, Mariam Sadaka, H.C. Tuan, Michael A. Mendicino, F. Metral, S. Murphy, Carlos Mazure, Y.C. See, Omar Zia, Ted R. White, Bich-Yen Nguyen, N. Cave, S. Venkatesan, Rode R. Mora, C.H. Chang, V. Van Der Pas, Ian Cayrefourcq, P. Beckage, J. Mogab, Yuan-Hung Chiu
Publikováno v:
Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005..
This paper describes the performance of multiple-V/sub T/, Triple-gate oxide SC-SSOI CMOS realized with Freescale's high-performance silicon-on-insulator (HiPerMOS-SOI) and SOITEC's advanced wafer-bonding technology. The thermal stability of wafer-bo
Fabrication and operation of sub-50 nm strained-Si on Si/sub 1-x/Ge/sub x/ Insulator (SGOI) CMOSFETs
Autor:
X.-D. Wang, S. Parsons, Mike Kottke, D. Tekleab, Aaron Thean, Bich-Yen Nguyen, P. Beckage, Mariam Sadaka, J. Mogab, S. Kalpat, C. Mazure, Ted R. White, Dharmesh Jawarani, Qianghua Xie, M. Zavala, T. Nguyen, M. Canonico, Ran Liu, Stefan Zollner, D. Eades, Rode R. Mora, Alexander L. Barr
Publikováno v:
2004 IEEE International SOI Conference (IEEE Cat. No.04CH37573).
First functional 45 nm SGOI CMOS devices on bonded SGOI substrates with T/sub SOI/