Výsledky vyhledávání - "Marco Zanuso"

AD-PLL for WiMAX with Digitally-Regulated TDC and Glitch Correction Logic

Autor: Salvatore Levantino, Carlo Samori, Davide Tasca, Paolo Madoglio, Marco Zanuso, Andrea L. Lacaita

Publikováno v: EURASIP Journal on Embedded Systems, Vol 2010, Iss 1, p 175764 (2010)
EURASIP Journal on Embedded Systems, Vol 2010 (2010)

This paper describes the design of an All-Digital Phase Locked Loop (AD-PLL) for wireless applications in the WiMAX 3.3–3.8 GHz bandwidth. The time/digital converter (TDC) sets the in-band noise and it may be responsible for the presence of spuriou

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_dedup___::2c1a59df591c2393151732ef9ff43d36
https://doi.org/10.1155/2010/175764

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Wohnhäuser Mailand, Via Laveno 6, 1961–64

Autor: Marco Zanuso

Publikováno v: Italomodern ISBN: 9783709108512

Die steinverkleideten Zwillingshauser erwecken den Eindruck von Massivitat und Gewicht. Im offenen Erdgeschoss erkennt man jedoch an den dunnen Saulen, dass das Gegenteil der Fall ist: Es handelt sich um leichte Stahlkonstruktionen, nur die Stiegenha

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::2324f9a0bb97056bc3ac4819348fe0c1
https://doi.org/10.1007/978-3-7091-0852-9_51

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Multipath adaptive cancellation of divider non-linearity in fractional-N PLLs

Autor: Marco Zanuso, Andrea L. Lacaita, Salvatore Levantino, Carlo Samori

Publikováno v: ISCAS

The mismatch-induced fractional spurs have so far limited the adoption of phase-interpolation-based fractional-N PLLs. Only recently a background cancellation technique, embedded in a digital fractional-N PLL, has faced this issue. In this paper, we

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_dedup___::72d8ac2690376e4ab1056d209a84bfce
https://doi.org/10.1109/iscas.2011.5937591

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Low-Power Divider Retiming in a 3-4GHz Fractional-N PLL

Autor: A.L. Lacaita, Marco Zanuso, Carlo Samori, Salvatore Levantino, Davide Tasca

The resynchronization of a frequency divider output is routinely used in the design of low-noise phase-locked loops (PLLs) in order to remove additional phase noise and avoid modulus-dependent nonlinearity. However, metastability issues cause PLLs to

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_dedup___::e7b82ccbbbf48783feeaedc1bff0978c
http://hdl.handle.net/11311/575449

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A 2.9-to-4.0GHz fractional-N digital PLL with Bang-Bang phase detector and 560fsrms integrated jitter at 4.5mw power

Autor: Davide, Tasca, Marco, Zanuso, Marzin, Giovanni, Levantino, Salvatore, Samori, Carlo, Lacaita, ANDREA LEONARDO

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=od______3731::db75a0efabae9297614b68c434c481c3
http://hdl.handle.net/11311/575450

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A Wideband 3.6 GHz Digital Delta-Sigma Fractional-N PLL With Phase Interpolation Divider and Digital Spur Cancellation

Autor: Salvatore Levantino, Marco Zanuso, A.L. Lacaita, Carlo Samori

A digital ΔΣ fractional-N frequency synthesizer for 4G communication standards is presented which is able to achieve wide loop bandwidth while producing low fractional spurs. The loop adopts a fractional-N divider based on a phase interpolator, all

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_dedup___::fc0fe3eb323004483df12258625eb2bc
http://hdl.handle.net/11311/575448

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A 3MHz-BW 3.6GHz digital fractional-N PLL with sub-gate-delay TDC, phase-interpolation divider, and digital mismatch cancellation

Autor: Carlo Samori, Andrea L. Lacaita, Salvatore Levantino, Marco Zanuso

Publikováno v: ISSCC

Digital Fractional-N PLLs allows easy cancellation of ΔΣ quantization noise and spurs [1], [2]. However, the actual results depend dramatically on the linearity of the time-to-digital converter (TDC). This paper presents a 3MHz bandwidth fractional

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_dedup___::c5ee38546c8c421cd1530bf0c55df1c1
http://hdl.handle.net/11311/570158

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Time-to-digital converter with 3-ps resolution and digital linearization algorithm

Autor: Salvatore Levantino, Andrea L. Lacaita, Marco Zanuso, Alberto Puggelli, Carlo Samori

Publikováno v: ESSCIRC

This paper presents a digital scrambling technique to improve the linearity of flash time-to-digital converters (TDCs) with sub-gate-delay time resolution. Thanks to this approach, a flash TDC using N time arbiters behaves as a quasi-stochastic TDC w

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_dedup___::acb925cc67877cce112997f26894923b
http://hdl.handle.net/11311/575454

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Time-to-Digital Converter for Frequency Synthesis based on a Digital Bang-Bang DLL

Autor: A.L. Lacaita, Salvatore Levantino, Paolo Madoglio, Marco Zanuso, Carlo Samori

Publikováno v: PP (2009): 1.
info:cnr-pdr/source/autori:Marco Zanuso, Paolo Madoglio, Salvatore Levantino, Carlo Samori, Andrea L. Lacaita/titolo:Time-to-Digital Converter for Frequency Synthesis based on a Digital Bang-Bang DLL/doi:/rivista:/anno:2009/pagina_da:1/pagina_a:/intervallo_pagine:1/volume:PP

This paper presents the design of a time-to-digital converter (TDC) suitable for a 3.5-GHz all-digital phase-lock loop (PLL). The converter is based on a digital bang-bang delay-lock loop, which allows constant resolution over process and temperature

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_dedup___::bc86798e091f4aec5b726637b75dde21
http://hdl.handle.net/11311/560588

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