Zobrazeno 1 - 10
of 12
pro vyhledávání: '"Marco Erstling"'
Autor:
Marco Erstling, Elammaran Jayamani, Kok Heng Soon, Lars Bergmann, Sanjay Shrirang Mane, Jagdish C. Patra
Publikováno v:
IEEE Transactions on Components, Packaging and Manufacturing Technology. 11:1258-1266
Recently, the circuit under pad (CUP) designs are getting very popular because they could save lots of silicon especially for high-density and high-complexity applications. Polysilicon is a material widely used in many electronic device components. W
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::14f6fcae28bd3205b2c11d8e67d4aff4
https://doi.org/10.1109/tcpmt.2021.3100100
https://doi.org/10.1109/tcpmt.2021.3100100
Autor:
Nico Hellwege, Marco Erstling, Timur Schafer, Theodor Hillebrand, Steffen Paul, Dagmar Peters-Drolshagen
Publikováno v:
Journal of Low Power Electronics. 13:135-147
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::bba4090959586000f34bcfcf08463a2d
https://doi.org/10.1166/jolpe.2017.1469
https://doi.org/10.1166/jolpe.2017.1469
Autor:
Peter Dimitrovici, Angela Fahr, Elammaran Jayamani, Jagdish Patra, Lars Bergmann, Sanjay Shrirang Mane, Soon Kok Heng, Raj Sekar Sethu, Marco Erstling
Publikováno v:
2019 IEEE 9th International Nanoelectronics Conferences (INEC).
The polysilicon is a material widely used in an many electronic components. When circuits are placed underneath the bond pads, it is expected that their electrical properties are not impacted by any kind of thermo-mechanical stress. This paper presen
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::509edd182b6975793cfce235c3c9308a
https://doi.org/10.1109/inec.2019.8853844
https://doi.org/10.1109/inec.2019.8853844
Autor:
Marco Erstling, Peter Lammert, Angela Fahr, Raj Sekar Sethu, Hansika Jayawardana, Lars Bergmann
Publikováno v:
2019 20th International Conference on Thermal, Mechanical and Multi-Physics Simulation and Experiments in Microelectronics and Microsystems (EuroSimE).
Harsh wafer level probing has a higher chance of causing inter metal dielectric (IMD) cracking compared to wire bonding. This work explores the stress induced by probing by utilizing dynamic Finite Element Analysis (FEA) structural mechanics simulati
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::e009d8367dc036cc330decccaa0a95de
https://doi.org/10.1109/eurosime.2019.8724542
https://doi.org/10.1109/eurosime.2019.8724542
Publikováno v:
Microelectronics Reliability. 64:259-265
The typical via layout in CMOS technology with AlCu-metallizations and tungsten via is cylindrical. Common vias have a size as small as possible in the related process. More challenging application, temperature and mission profiles require higher rob
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::f37e46162df802c1bb7b052030441edd
https://doi.org/10.1016/j.microrel.2016.07.136
https://doi.org/10.1016/j.microrel.2016.07.136
Publikováno v:
2017 18th International Conference on Thermal, Mechanical and Multi-Physics Simulation and Experiments in Microelectronics and Microsystems (EuroSimE).
The metal layout design influences the reliability of the metallization in semiconductor products. An optimized design of the interconnect stack can help to reduce the incidence of dielectric and passivation cracking during Joule heating of the metal
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::2598a16152a7a591e2c2f57ecd89350b
https://doi.org/10.1109/eurosime.2017.7926226
https://doi.org/10.1109/eurosime.2017.7926226
Publikováno v:
2017 IEEE International Reliability Physics Symposium (IRPS).
The use of a thick Copper layer on top of an AlCu-metallization stack instead of a common thick Aluminium layer triggers the need for a change in the reliability characterization, the test structure layouts and reliability test methods. The failure a
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::dc9d154597afb8447b81fd7abf9492ab
https://doi.org/10.1109/irps.2017.7936377
https://doi.org/10.1109/irps.2017.7936377
Publikováno v:
Microelectronics Reliability. :113333
Polysilicon is an integral part of many devices in all CMOS processes. Circuit Under Pad (CUP) devices are required to have consistent and accurate electrical performance just like any other device. This paper presents an investigation on stress impa
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::b7a85a63dfa5b3066de7e69101b76d86
https://doi.org/10.1016/j.microrel.2019.06.025
https://doi.org/10.1016/j.microrel.2019.06.025
Autor:
Steffen Paul, Marco Erstling, Theodor Hillebrand, Nico Hellwege, Dagmar Peters-Drolshagen, Timur Schafer
Publikováno v:
PATMOS
In this paper a tool based on the g m /I D -methodology is presented to provide information on operating point-dependent degradation in integrated circuits caused by NBTI and HCI during early design stages. The advantage of the presented GMID-Tool is
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::5b655aa6e5f7e18274b7e5786d9c98f6
https://doi.org/10.1109/patmos.2016.7833678
https://doi.org/10.1109/patmos.2016.7833678
Autor:
Verena Hein, Marco Erstling
Publikováno v:
2016 Pan Pacific Microelectronics Symposium (Pan Pacific).
Monitoring Wafer Level Reliability (WLR) tests are common to guarantee process stability and homogeneity. The test cost and test time efficiency are very important because of the high number of monitoring tests. Interconnects like metal lines and via
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::7d3e143ed92550202153232faeda4ae2
https://doi.org/10.1109/panpacific.2016.7428412
https://doi.org/10.1109/panpacific.2016.7428412