Zobrazeno 1 - 5
of 5
pro vyhledávání: '"Marcel Lugthart"'
Publikováno v:
2022 IEEE International Symposium on Phased Array Systems & Technology (PAST).
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::780c32dddcf051e6816c72df0fbc963a
https://doi.org/10.1109/past49659.2022.9975074
https://doi.org/10.1109/past49659.2022.9975074
Autor:
Christopher M. Ward, Marcel Lugthart, Jan Roelof Westra, Klaas Bult, Jan Mulder, F.M.L. van der Goes, Chi-Hung Lin, R.J. van de Plassche, Erol Arslan, D. Kruse
Publikováno v:
IEEE Journal of Solid-State Circuits. 39:2116-2125
This paper presents an 8-b two-step subranging analog-to-digital (ADC) using interpolation, averaging, offset compensation, and pipelining techniques to accomplish an effective number of bits of 7.6 b at 125 MSample/s. The 0.13-/spl mu/m CMOS ADC occ
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::2020a6c5d7dab73ea6021e543138de3f
https://doi.org/10.1109/jssc.2004.836235
https://doi.org/10.1109/jssc.2004.836235
Publikováno v:
CICC
A low-power, small-area transceiver PHY that supports SFI-5.1 is fabricated in standard 40 nm CMOS, supporting rates up to 50 Gb/s. The combined active core area of the receiver (RX) and transmitter (TX) occupies only 0.08 mm2 per lane. The RX can ha
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::b107212efb837e1175f8f5ef40dcf106
https://doi.org/10.1109/cicc.2011.6055361
https://doi.org/10.1109/cicc.2011.6055361
Autor:
F.M.L. van der Goes, Marcel Lugthart, Christopher M. Ward, R.J. van de Plassche, Klaas Bult, Chi-Huang Lin, Ovidiu Bajdechi, Jan Roelof Westra, D. Kruse, Erol Arslan, Jan Mulder
Publikováno v:
Analog Circuit Design ISBN: 9781402051852
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::ddae6d2c767a52533261200bf86227e8
https://doi.org/10.1007/1-4020-5186-7_4
https://doi.org/10.1007/1-4020-5186-7_4
Autor:
Jan Mulder, Klaas Bult, Christopher M. Ward, Chi-Hung Lin, Erol Arslan, R.J. van de Plassche, Jan Roelof Westra, F.M.L. van der Goes, D. Kruse, Marcel Lugthart
Publikováno v:
2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519).
An 8b subranging ADC uses interpolation, averaging, offset compensation and pipelining techniques to accomplish 7.6b ENOB at 125MS/s. The 0.13/spl mu/m CMOS ADC occupies 0.09mm/sup 2/ and consumes 21 mW.
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::7dc2458803deb2402f2e791103bcb458
https://doi.org/10.1109/isscc.2004.1332693
https://doi.org/10.1109/isscc.2004.1332693